DS1050
NOTES:
1.
2.
3.
4.
5.
6.
All voltages are referenced to ground.
I
CC
specified with outputs open.
I/O pins of fast mode devices must not obstruct the SDA and SCL lines if V
CC
is switched off.
Address Inputs, A0, A1, and A2, should be tied to either V
CC
or GND depending on the desired
address selections.
I
STBY
specified for V
CC
between 3.0V and 5.0V, control port logic pins are driven to the appropriate
logic levels.
A fast mode device can be used in a standard mode system, but the requirement
t
SU:DAT
> 250ns must then be met. This will automatically be the case if the device does not stretch
the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line t
RMAX
+ t
SU:DAT
= 1000 + 250=1250ns before the SCL
line is released.
After this period, the first clock pulse is generated.
The maximum t
SU:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the
SCL signal.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
V
IH MIN
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
C
B
– total capacitance of one bus line in picofarads, timing referenced to (0.9)(V
CC
) and (0.1)(V
CC
).
A PWM output duty cycle change will occur with 2 periods of the output frequency when a change is
initiated.
The absolute frequency output of the PWM can be expected to fall within a
±20%
range from the
nominal specified value of the device.
The DS1050 is a 5-bit PWM. The output duty cycles of the device range from 0% to 100% in step
sizes of 3.125%. The “Set PWM Duty Cycle 100%” allows the PWM output to be set to full-on.
Absolute Linearity is used to compare measured duty cycle against expected duty cycle as
determined by the DAC setting. The DS1050 is specified to provide an absolute linearity of
±0.5
LSB.
Relative Linearity is used to determine the change in duty cycle between adjacent or successive duty
cycle settings. The DS1050 is specified to provide a relative linearity specification of
±0.25
LSB.
7.
8.
9.
10.
11.
12.
13.
14.
15.
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DALLAS [ DALLAS SEMICONDUCTOR ]
