DS1040
t
RISE
(Input Rise Time):
The elapsed time between the 20% and the 80% point on the leading edge of
the input pulse.
t
FALL
(Input Fall Time):
The elapsed time between the 80% and the 20% point on the trailing edge of
the input pulse.
t
D
(Intrinsic Delay):
The elapsed time between the 1.5 point on the leading edge of the input trigger
pulse and the 1.5V point on the leading edge of output pulse.
t
PU
(Power-up Time):
After V
CC
is valid, the time required before timing specifications is within
tolerance.
TEST SETUP DESCRIPTION
Figure 4 illustrates the hardware configuration used for measuring the timing parameters on the DS1040.
The input waveform is produced by a precision pulse generator under software control. The intrinsic
delay is measured by a time interval counter (20 ps resolution) connected between the input and each
output. Outputs are selected and connected to the counter by a VHF switch control unit. Width
measurements are made by directing both the start and stop functions of the counter to the same output.
All measurements are fully automated, with each instrument controlled by a central computer over an
IEEE 488 bus.
TEST CONDITIONS
Input:
Ambient Temperature:
Supply Voltage (V
CC
):
Input Pulse:
Source Impedance:
Rise and Fall Time:
Pulse Width:
Period:
25°C + 3°C
5.0V + 0.1V
High = 3.0V + 0.1V
Low = 0.0V + 0.1
50 ohm max.
3.0 ns max. (measured
between 0.6V and 2.4)
500 ns (1
µs
for -500)
1
µs
(2
µs
for -500)
Output:
The output is loaded with a 74F04. Delay is measured at the 1.5V level on the rising and falling edge.
Note:
Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
6 of 6
DALLAS [ DALLAS SEMICONDUCTOR ]
