DS1023
TIMING DIAGRAM: SILICON DELAY LINE Figure 9
AC ELECTRICAL CHARACTERISTICS -
DS1023-025 Delay Specifications
(TA = 0°C to 70°C; VCC = 5V ±=5%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Step Zero Delay
-absolute
-wrt REF
Reference Delay
Delay Step Size
tD0
tDREF0
tREF
16.5
-1.5
18
22
0
22
ns
ns
ns
ns
1, 13
2, 14
3, 13
4
-2
0
tSTEP
0.25
0.75
Maximum Delay
-absolute
-wrt REF
Delay Matching, Rising Edge
to Falling Edge
tDMAX
tDREF
75
60
-1
80
63.75
89
67.5
+1
ns
ns
ns
5, 13
6, 14
15
Integral Non-linearity
(deviation from straight line)
OUT Delta Delay
IN High to PWM High
Minimum PWM Output
Pulse Width
Minimum Input Pulse Width
Minimum Input Period
Input Rise and Fall Times
terr
tINV0
tPWM0
-1
0
0
1
16.5
+1
2
22
ns
ns
ns
7
8
9, 13
tPWM
tWI
5
20
40
0
ns
ns
ns
µs
10
11
12
16
tr, tf
1
10 of 16