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DS1020-15 参数 Datasheet PDF下载

DS1020-15图片预览
型号: DS1020-15
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程的8位硅延迟线 [Programmable 8-Bit Silicon Delay Line]
分类和应用: 延迟线逻辑集成电路光电二极管
文件页数/大小: 9 页 / 193 K
品牌: DALLAS [ DALLAS SEMICONDUCTOR ]
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DS1020  
Programmable 8-Bit  
Silicon Delay Line  
www.dalsemi.com  
FEATURES  
PIN ASSIGNMENT  
All-silicon time delay  
IN  
E
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
VCC  
OUT  
S
Models with 0.15 ns, 0.25 ns, 0.5 ns, 1 ns,  
and 2 ns steps  
IN  
E
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
VCC  
OUT  
S
Programmable using 3-wire serial port or  
8-bit parallel port  
Q/PO  
P1  
P7  
P6  
C
Q/PO  
P1  
Leading and trailing edge accuracy  
Standard 16-pin DIP or 16-pin SOIC  
Economical  
P7  
P6  
C
P2  
P2  
P3  
P3  
P4  
P5  
D
P4  
P5  
D
Auto-insertable, low profile  
Low-power CMOS  
GND  
GND  
TTL/CMOS-compatible  
Vapor phase, IR and wave solderable  
DS1020 16-pin DIP (300-mil) DS1020S 16-pin SOIC (300-mil)  
See Mech. Drawings Section See Mech. Drawings Section  
PIN DESCRIPTION  
IN  
- Delay Input  
P0-P7  
GND  
OUT  
VCC  
S
- Parallel Program Pins  
- Ground  
- Delay Output  
- +5 Volts  
- Mode Select  
- Enable  
E
C
- Serial Port Clock  
- Serial Data Output  
- Serial Data Input  
Q
D
DESCRIPTION  
The DS1020 Programmable 8-Bit Silicon Delay Line consists of an 8-bit, user-programmable CMOS  
silicon integrated circuit. Delay values, programmed using either the 3-wire serial port or the 8-bit  
parallel port, can be varied over 256 equal steps. The fastest model (-15) offers a maximum delay of  
48.25 ns with an incremental delay of 0.15 ns, while the slowest model (-200) has a maximum delay of  
520 ns with an incremental delay of 2 ns. All models have an inherent (step-zero) delay of 10 ns. After  
the user-determined delay, the input logic state is reproduced at the output without inversion. The  
DS1020 is TTL- and CMOS-compatible, capable of driving 10 74LS-type loads, and features both rising  
and falling edge accuracy.  
The all-CMOS DS1020 integrated circuit has been designed as a reliable, economic alternative to hybrid  
programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a space-saving  
surface mount 16-pin SOIC.  
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