DS1013
NOTES:
1. All voltages are referenced to ground.
2. Measured with outputs open.
3. V
CC
= 5V @ 25°C. Delays accurate on both rising and falling edges within ±2 ns for -10 to -60, ±3%
for -70 to 100 and ±5% for -150 and longer delays.
4. See “Test Conditions” section.
5. The combination of temperature variations from 25°C to 0°C or 25°C to 70°C and voltage variations
from 5.0V to 4.75V or 5.0V to 5.25V may produce an additional delay shift of ±1.5 ns or ±3%,
whichever is greater.
6. All output delays tend to vary unidirectionally over temperature or voltage ranges (i.e., if OUT 1
slows down, all other outputs also slow down).
7. Period specifications may be exceeded; however, accuracy will be application-sensitive (decoupling,
layout, etc.).
TERMINOLOGY
Period:
The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
t
WI
(Pulse Width):
The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
t
RISE
(Input Rise Time):
The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
t
FALL
(Input Fall Time):
The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
t
PLH
(Time Delay, Rising):
The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
t
PHL
(Time Delay, Falling):
The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
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DALLAS [ DALLAS SEMICONDUCTOR ]
