DS1012
NOTES:
1. All voltages are referenced to ground.
2. Measured with outputs open, minimum period. I
CC1
(max.) for any value of Period can be calculated using the
formula:
I
CC1
(max.) = 840/Period + I
CC2
where I
CC1
, I
CC2
in mA, Period in ns
Example: If Period = 50 ns then
I
CC1
(Max) = 840/50 + 0.01 = 16.81 mA
3. V
CC
= 5V @ 25°C. Delays referenced to leading (input rising) edges are accurate within
±1.5
ns for values
between 3 to 10 ns and
±2
ns for values between 11 to 40 ns. Delays referenced to trailing (input falling)
edges will typically equal the corresponding leading edge delay within
±1
ns.
4. See the section entitled “Test Conditions.”
5. For the quiescent mode, both inputs must meet the conditions
0.3V > V
I
or VI > V
CC
- 0.3
6. For specified accuracy, t
WI
(min) is the longer of 3(t
D1
), 3(t
D2
), 3(t
D3
), or 3(t
D4
). Pulse doublers designed for
single frequency use will meet specified accuracies at 50% duty cycle; i.e., 2(t
WI
) = 1/FREQ = PERIOD. Cus-
toms will be adjusted to be accurate at customer input width specifications when t
WI
is longer than t
D1
, t
D2
,
t
D3
, and t
D4
.
7. On power-up, the DS1012 will supply timing and logic functions with specified accuracy as soon as V
CC
achieves nominal value.
021798 7/7
DALLAS [ DALLAS SEMICONDUCTOR ]
