DS1007
LOGIC DIAGRAM Figure 1
PART NUMBER DELAY TABLE (tPLH) Table 1
PART #
OUT1
OUT2
OUT3
OUT4
OUT5
9ns
12
OUT6
13ns
14
OUT7
DS1007-1
DS1007-2
DS1007-3
DS1007-4
DS1007-5
DS1007-6
DS1007-7
DS1007-8
DS1007-9
DS1007-10
DS1007-11
DS1007-12
DS1007-13
DS1007-14
3ns
4
3
4
5
6
7
8
9
10
3
3
3
7
4ns
6
3
4
5
6
7
8
9
10
4
4
4
7
5ns
8
3
4
5
6
7
8
9
10
6
6
6
7
6ns
10
3
4
5
6
7
8
9
10
8
8
8
7
18ns
16
10
12
15
20
25
30
35
40
14
20
20
9
10
12
15
20
25
30
35
40
10
10
12
9
10
12
15
20
25
30
35
40
12
15
15
9
Custom delays available. Out 1 through Out 4 can be custom set from 3 to 10 ns (leading edge only
accuracy). Out 5 through Out 7 can be set from 9 to 40 ns (both leading and trailing edge accuracy).
2 of 6
DALLAS [ DALLAS SEMICONDUCTOR ]
