Spec. No. : C504A3
Issued Date : 2003.03.21
Revised Date :
CYStech Electronics Corp.
cystek
Page No. : 7/9
Test Circuit-Small-Signal Gain and Phase
Test Circuit-Stability
R
OUT
Iz
Iz
R1
R2
μ
10
F
15k
232
PL432
CL
PL432
8.25k
GND
Applications Information - Stability
Selection of load capacitance when using PL432 as a shunt regulator
When the PL432 is used as a shunt regulator, two options for selection of CL(see diagram on page 6)
are recommended for optimal stability:
1) No load capacitance across the device, decouple at the load.
2) Large capacitance across the device, optimal decoupling at the load.
The reason for this is that PL432 exhibits instability with capacitances in the range of 10nF to 1μF
(approx.) at light cathode currents(up to 3mA typical). The device is less stable the lower the cathode
voltage has been set for. Therefore while the device will be perfectly stable operating at a cathode
current of (say) 10mA with a 0.1μF capacitor across it, it will oscillate transiently during start-up as the
cathode current passes through the instability region. Selecting a very low (or preferably, no) capaci-
tance, or alternatively a high capacitance(such as 10μF) will avoid this issue altogether. Since the user
will probably wish to have local decoupling at the load anyway, the most cost effective method is to use
no capacitance at all directly across the device. PCB trace/via resistance and inductance prevent the
local load decoupling from causing the oscillation during the transient start-up phase.
Note : if the PL432 is located right at the load, so the load decoupling capacitor is directly across it, then
this capacitor will have to be ≤1nF or ≥10μF.
PL432XA3/N3
CYStek Product Specification
CYSTEKEC [ CYSTECH ELECTONICS CORP. ]
