ES51999
4 3/4 and 5 3/4 A/D AUTO
(4) zero integration phase (ZI)
Normally, the time ratios of these four phases, AZ, INT, DINT and ZI to the entire
measurement cycle are 20%, 20%, 44% and 16% respectively. However the actual
duration of each phase depends on conversion rate. The time of each conversion rate are
shown in the table below in which voltage/current (without PEAK HOLD or frequency),
and diode measurement use this conversion time.
C[0:1]
01
CR (times/sec)
ZI (ms)
AZ (ms)
10
INT (ms)
10
DINT (ms)
20
10
5
8
22
44
00
16
32
80
20
20
10
40
40
88
11
2
100
100
220
Note: Vref = -200 mV.
(3) Component Value Selection for ADC
For various application requirements on conversion rate and input full range, we
suggest nominal values for external components of ADC in Figure 2.1 to obtain better
performance. Under default condition with operating clock = 4 MHz:
(1) conversion rate = 10 times/sec
(2) reference voltage = -200 mV
(3) input signal full scale = 440 mV (sensitivity = 10 uV)
we suggest that Cint = 33 nF, Buf = 200 kΩ, BufX10=20K
If a user selects a different conversion rate rather than default, the integration capacitor
Cint value must be changed according to the following rule for better performance:
Cint × (conversion rate) = (33 nF) × (10 times/sec).
It is important that the actual Cint value should be no less than the nominal value. A
smaller Cint reduces the input full range. However a larger Cint might have weaker noise
immunity than the suggested one.
A user could enlarge the input full range by changing reference voltage (Vref) and the
amount of integration resistor (Buf and Raz). For example, if Vref, Buf and Raz are
enlarged as twice than the default values then the input full range becomes 880 mV. The
input full range can be enlarged up to 1.1V (2.5 times than the default case). We list
general rules in below which might be helpful in determining component values.
Buf / (reference voltage) = 200 kΩ / (-200 mV)
(4) Voltage Measurement
11
07/07/06
CYRUSTEK [ Cyrustek corporation ]
