ES51966
4 3/4 and 5 3/4 A/D (Peak &Cap)
D0<0:19> Conversion result of voltage or current measurement.
D1<0:17> Conversion result of frequency measurement.
- Frequency (“110”) measurement:
OL
0
UL
1
BATT
2
D0<0:19> (20 bits) D1<0:17> (18 bits)
22 23 40
D2<0:5> (6 bits)
41 46
3
~
~
~
OL Overflow when in 40, 400 and 4000Hz ranges.
UL Underflow when in 40, 400 and 4000Hz ranges.
BATT ‘H’ for battery-low indication.
D0<0:19>, D1<0:17>, D2<0:5> Please see the description in frequency and duty
cycle measurement.
(2) Dual Slope A/D—four phases timing
The ES51966’s measurement cycle contains four phases, ZI, AZ, INT, and DINT.
The timing will be changed as conversion rate changed. There are some examples as
follow, and the others are alike.
ES51966 is a dual-slope analog-to-digital converter (ADC). Figure 2.1 is a
structure of dual-slope integrator. Its measurement cycle has two distinct phases: input
signal integration (INT) phase and reference voltage integration (DINT) phase.
In INT phase, the input signal is integrated for a fixed time period, then A/D enters
DINT phase in which an opposite polarity constant reference voltage is integrated until
the integrator output voltage becomes to zero. Since both the time for input signal
integration and the reference voltage are fixed, the de-integration time is proportional to
the input signal. Hence, we can define the mathematical equation about input signal,
reference voltage integration (see Figure 2.1):
TINT
1
1
VIN (t)dt =
×VREF ×TDINT
∫
0
Buf × C int
Buf × C int
where, VIN (t) = input signal
VREF = reference voltage
TINT = integration time (fixed)
TDINT = de-integration time (proportional toVIN (t) )
If VIN (t) is a constant, we can rewrite above equation:
TINT
TDINT
=
×VIN
VREF
Besides the INT phase and DINT phase, ES51966 exploits auto zero (AZ) phase and zero
10
06/04/25
CYRUSTEK [ Cyrustek corporation ]
