ES5129
4-1/2 digit with LCD
10
11
12
13
14
15
16
A4, G4, D4
F4, E4, DP4
BP3
O Output to LCD segment.
O Output to LCD segment.
O LCD backplane signal
O LCD backplane signal
O LCD backplane signal
BP2
BP1
VDISP
DP4/OR
P Negative supply for display drivers.
I/O Input: Turns on most significant decimal point when HI.
Output: Pulled HI when result count exceeds ±19,999.
O TEST pin. Not connect.
17
18
TEST2
DP3/UR
I/O Input: Turn on the 2nd significant decimal point when HI.
Output: Pulled HI when result count is less than ±1,000.
19 LATCH/HOLD I/O Input: when floating, ES5129 operates in the free-run mode.
When pulled high, the last display reading is held. When
pulled LO, the result counter contents are shown
incrementing during the de-integrate phase of cycle.
Output: Negative going edge occurs when the data latches are
upgraded. Can be used as a converter status signal.
20
21
22
23
24
V-
V+
CAZ
CINT
P Negative power supply terminal
P Positive power supply terminal
I/O Integrator amplifier input
I/O Integrator amplifier output
CONTINUITY I/O Input: when LO, continuity flag on the display is off. When
HI, continuity flag is on.
Output: HI when voltage between inputs is less than +200mV
LO when voltage between inputs is more than +200mV.
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
COMMON
CREF+
CREF-
NC
BUFFER
IN_LO
IN_HI
O Set common-mode voltage of 3.2V below V+.
I/O Positive connection to external reference capacitor
I/O Negative connection to external reference capacitor
O Buffer amplifier output
I Negative input voltage terminal
I Positive input voltage terminal
REF_HI
REF_LO
DGND
RANGE
DP2
I Positive reference voltage terminal
I Negative reference voltage terminal
O Ground reference for digital section
I Pulled HIGH externally for 2V scale.
I When HI, decimal point 2 will be on.
I When HI, decimal point 1 will be on.
I/O Output of first clock inverter. Input of second clock inverter.
I Reduce the integration time to 1/10 when RANGE is set to
high. The polarity of ADC will be ignored also.
I/O Input of first clock inverter.
DP1
OSC2
INT100
40
41
42
43
44
OSC1
OSC3
ANNUNC
I/O Output of second clock inverter.
O Backplane squarewave output for driving annunctors.
B1, C1, CONT O Output to LCD segment.
A1, G1, D1
O Output to LCD segment.
5
07/03/01
CYRUSTEK [ Cyrustek corporation ]
