ES5120
3 3/4 DIGIT A/D CONVERTER
comparator offset voltage error compensation. A voltage
established on CAZ then compensates for internal device
offset voltages during the measurement cycle.
The Auto Zero phase residual is typically 10 to 15μA.
(2) Signal Integration Phase
Upon completion of the Auto Zero phase, the Auto Zero
loop is opened and the internal differential inputs connect
+
-
to VIN and VIN . The differential input signal is then
integrated for a fixed time period, which in the ES5120 is
2000 counts (4000 clock periods). The externally set clock
frequency is divided by two before clocking the internal
counters. The integration time period is :
4000
TINT＝―――― ＝ 2000 Counts
fosc
The differential input voltage must be within the device
common-mode range when the converter and measured
system share the same power supply common (ground). If
the converter and measured system do not share the same
power supply common as in battery powered applications,
VIN- should be tied to Analog Common.
Polarity is determined at the end of signal integration phase.
The sign bit is a "true polarity" indication in that signals
less than 1 LSB are correctly determined. This allows
precision null detection which is limited only by device
noise and Auto Zero residual offsets.
CYRUSTEK [ Cyrustek corporation ]
