W312-02
FTG for VIA™ K7 Series Chipset with
Programmable Output Frequency
Features
• Single chip FTG solution for VIA™ K7 Series chipsets
• Programmable clock output frequency with less than
1 MHz increment
• Integrated fail-safe Watchdog timer for system
recovery
• Automatically switch to HW selected or SW
programmed clock frequency when watchdog timer
time-out
• Capable of generate system RESET after a watchdog
timer time-out occurs or a change in output frequency
via SMBus interface
• Support SMBus byte read/write and block read/ write
operations to simplify system BIOS development
• Vendor ID and Revision ID support
• Programmable drive strength for PCI output clocks
• Programmable output skew between CPU, AGP and PCI
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Low jitter and tightly controlled clock skew
• Two pairs of differential CPU clocks
• Eleven copies of PCI clocks
• Three copies of 66-MHz outputs
• Two copies of 48-MHz outputs
• Three copies of 14.31818-MHz reference clocks
• One RESET output for system recovery
• Power management control support
Key Specifications
CPU Outputs Cycle-to-cycle Jitter: ............................. 250 ps
48-MHz, 3V66, PCI Outputs
Cycle-to-cycle Jitter: .................................................... 500 ps
CPU, 3V66 Output Skew:............................................ 200 ps
48-MHz Output Skew: ................................................. 250 ps
PCI Output Skew:........................................................ 500 ps
Block Diagram
VDD_REF
Pin Configuration
REF2
REF1/FS1*
REF0/FS0*
[1]
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF0/FS0*
REF1/FS1*
REF2
REF_STOP#*
AGP_STOP#*
GND_CPU
CPUT0
CPUC0
VDD_CPU
CPUT_CS
CPUC_CS
GND_CPU
CPU_STOP#*
PCI_STOP#*
PD#*
VDD_CORE
GND_CORE
SDATA
SCLK
GND_AGP
AGP2
AGP1
AGP0
VDD_AGP
X1
X2
XTAL
OSC
PLL REF FREQ
VDD_CPU
Divider,
Delay,
and
Phase
Control
Logic
2
CPUT0,CPUC0
CPUT_CS,CPUC_CS
VDD_AGP
AGP0:2
SDATA
SCLK
SMBus
Logic
(FS0:4)
3
VDD_PCI
PCI0/SEL24_48#*
PLL 1
PD#
CPU_STOP#
PCI_STOP#
AGP_STOP#
REF_STOP#
5
PCI1:8
PCI9_E
RST#
VDD_48MHz
48MHz/FS3*
VDD_REF
GND_REF
X1
X2
VDD_48MHz
*FS2/48MHz
*FS3/24_48MHz
GND_48MHz
*FS4/PCI_F
*SEL24_48#/PCI0
PCI1
GND_PCI
PCI2
PCI3
VDD_PCI
PCI4
PCI5
PCI6
GND_PCI
PCI7
PCI8
PCI9_E
VDD_PCI
RST#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PLL2
/2
SEL24_48#*
24_48MHz/FS4*
Note:
1. Internal 100K pull-up resistors present on inputs marked with *. De-
sign should not rely solely on internal pull-up resistor to set I/O pins
HIGH.
Cypress Semiconductor Corporation
Document #: 38-07259 Rev. *C
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised April 28, 2005
W312-02
CYPRESS [ CYPRESS SEMICONDUCTOR ]
