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W255H 参数 Datasheet PDF下载

W255H图片预览
型号: W255H
PDF下载: 下载PDF文件 查看货源
内容描述: 200 - MHz的24 -输出缓冲器4 DDR或3 SDRAM DIMM, [200-MHz 24-Output Buffer for 4 DDR or 3 SDRAM DIMMS]
分类和应用: 时钟驱动器逻辑集成电路光电二极管动态存储器双倍数据速率
文件页数/大小: 10 页 / 256 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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W255
200-MHz 24-Output Buffer for 4 DDR
or 3 SDRAM DIMMS
Features
• One input to 24-output buffer/driver
• Supports up to 4 DDR DIMMs or 3 SDRAM DIMMS
• One additional output for feedback
• SMBus interface for individual output control
• Low skew outputs (< 100 ps)
• Supports 266-, 333-, and 400-MHz DDR SDRAM
• Dedicated pin for power management support
• Space-saving 48-pin SSOP package
Functional Description
The W255 is a 3.3V/2.5V buffer designed to distribute
high-speed clocks in PC applications. The part has 24 outputs.
Designers can configure these outputs to support four unbuf-
fered DDR DIMMS or to support three unbuffered standard
SDRAM DIMMs and two DDR DIMMS. The W255 can be used
in conjunction with the W250 or similar clock synthesizer for
the VIA Pro 266 chipset.
The W255 also includes an SMBus interface which can enable
or disable each output clock. On power-up, all output clocks
are enabled (internal pull up).
Block Diagram
FBOUT
BUF_IN
DDR0T_SDRAM10
DDR0C_SDRAM11
DDR1T_SDRAM0
DDR1C_SDRAM1
DDR2T_SDRAM2
DDR2C_SDRAM3
DDR3T_SDRAM4
DDR3C_SDRAM5
DDR4T_SDRAM6
DDR4C_SDRAM7
DDR5T_SDRAM8
DDR5C_SDRAM9
DDR6T
DDR6C
DDR7T
DDR7C
DDR8T
DDR8C
DDR9T
DDR9C
DDR10T
PWR_DWN#
Power Down Control
Pin Configuration
[1]
SSOP
Top View
FBOUT
VDD3.3_2.5
GND
DDR0T_SDRAM10
DDR0C_SDRAM11
DRR1T_SDRAM0
DDR1C_SDRAM1
VDD3.3_2.5
GND
DDR2T_SDRAM2
DDR2C_SDRAM3
VDD3.3_2.5
BUF_IN
GND
DDR3T_SDRAM4
DDR3C_SDRAM5
VDD3.3_2.5
GND
DDR4T_SDRAM6
DDR4C_SDRAM7
DDR5T_SDRAM8
DDR5C_SDRAM9
VDD3.3_2.5
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SDATA
SMBus
Decoding
SCLOCK
DDR10C
DDR11T
SEL_DDR*
VDD2.5
GND
DDR11T
DDR11C
DDR10T
DDR10C
VDD2.5
GND
DDR9T
DDR9C
VDD2.5
PWR_DWN#*
GND
DDR8T
DDR8C
VDD2.5
GND
DDR7T
DDR7C
DDR6T
DDR6C
GND
SCLK
SEL_DDR
DDR11C
Note:
1. Internal 100K pull-up resistors present on inputs marked
with *. Design should not rely solely on internal pull-up resistor
to set I/O pins HIGH.
Cypress Semiconductor Corporation
Document #: 38-07255 Rev. *D
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised April 28, 2005