CYWUSB6932
CYWUSB6934
Addr: 0x09
7
6
5
REG_RX_DATA_A
4
Data
3
2
1
Default: 0x00
0
Figure 7-8. Receive SERDES Data A
Bit
Name
Description
7:0
Data
Received Data for Channel A. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3,
followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
Addr: 0x0A
7
6
5
REG_RX_VALID_A
4
Valid
3
2
1
Default: 0x00
0
Figure 7-9. Receive SERDES Valid A
Bit
Name
Description
7:0
Valid
These bits indicate which of the bits in the Receive SERDES Data A register (Reg 0x09) are valid. A “1” indicates that the
corresponding data bit is valid for Channel A.
If the Valid Data bit is set in the Receive Interrupt Status register (Reg 0x08) all eight bits in the Receive SERDES Data A register
(Reg 0x0A) are valid. Therefore, it is not necessary to read the Receive SERDES Valid A register (Reg 0x0C). This register is
read-only.
Addr: 0x0B
7
6
5
REG_RX_DATA_B
4
Data
3
2
1
Default: 0x00
0
Figure 7-10. Receive SERDES Data B
Bit
Name
Description
7:0
Data
Received Data for Channel B. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3,
followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
Figure 7-11. Receive SERDES Valid B
Addr: 0x0C
7
6
5
REG_RX_VALID_B
4
Valid
3
2
1
Default: 0x00
0
Bit
Name
Description
7:0
Valid
These bits indicate which of the bits in the Receive SERDES Data B register (Reg 0x0B) are valid. A “1” indicates that the
corresponding data bit is valid for Channel B.
If the Valid Data bit is set in the Receive Interrupt Status register (0x08) all eight bits in the Receive SERDES Data B register
(Reg 0x0B) are valid. Therefore, it is not necessary to read the Receive SERDES Valid B register (Reg 0x0C). This register is
read-only.
Document 38-16007 Rev. *I
Page 13 of 30
CYPRESS [ CYPRESS SEMICONDUCTOR ]
