CY8C29x66 Final Data Sheet
3. Electrical Specifications
3.4
3.4.1
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C
≤
T
A
≤
85°C, or 3.0V to 3.6V and -40°C
≤
T
A
≤
85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Note
See the individual user module data sheets for information on maximum frequencies for user modules.
Table 3-17: AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
F
IMO24
Internal Main Oscillator Frequency for 24 MHz
23.4
24
24.6
a,b,c
MHz
Trimmed for 5V or 3.3V operation using
factory trim values. See the figure on
page 19. SLIMO Mode = 0.
Trimmed for 5V or 3.3V operation using
factory trim values. See the figure on
page 19. SLIMO Mode = 1.
F
IMO6
Internal Main Oscillator Frequency for 6 MHz
5.75
6
6.35
a,b,c
MHz
F
CPU1
F
CPU2
F
48M
F
24M
F
32K1
F
32K2
F
PLL
Jitter24M2
T
PLLSLEW
T
PLLSLEWLOW
T
OS
T
OSACC
CPU Frequency (5V Nominal)
CPU Frequency (3.3V Nominal)
Digital PSoC Block Frequency
Digital PSoC Block Frequency
Internal Low Speed Oscillator Frequency
External Crystal Oscillator
PLL Frequency
24 MHz Period Jitter (PLL)
PLL Lock Time
PLL Lock Time for Low Gain Setting
External Crystal Oscillator Startup to 1%
External Crystal Oscillator Startup to 100 ppm
0.93
0.93
0
0
15
–
–
–
0.5
0.5
–
–
24
12
48
24
32
32.768
23.986
–
–
–
250
300
24.6
a,b
12.3
b,c
49.2
a,b,d
24.6
b, d
64
–
–
600
10
50
500
600
MHz
MHz
MHz
MHz
kHz
kHz
MHz
ps
ms
ms
ms
ms
The crystal oscillator frequency is within 100 ppm
of its final value by the end of the T
osacc
period.
Correct operation assumes a properly loaded 1 uW
maximum drive level 32.768 kHz crystal. 3.0V
≤
Vdd
≤
5.5V, -40
o
C
≤
T
A
≤
85
o
C.
Refer to the AC Digital Block Specifica-
tions below.
Accuracy is capacitor and crystal dependent.
50% duty cycle.
A multiple (x732) of crystal frequency.
Jitter32k
T
XRST
DC24M
Step24M
Fout48M
Jitter24M1
F
MAX
T
RAMP
32 kHz Period Jitter
External Reset Pulse Width
24 MHz Duty Cycle
24 MHz Trim Step Size
48 MHz Output Frequency
24 MHz Period Jitter (IMO)
Maximum frequency of signal on row input or row output.
Supply Ramp Time
–
10
40
–
46.8
–
–
0
100
–
50
50
48.0
600
–
–
12.3
–
–
60
–
49.2
a,c
ns
μ
s
%
kHz
MHz
ps
MHz
μ
s
Trimmed. Utilizing factory trim values.
a.
b.
c.
d.
4.75V < Vdd < 5.25V.
Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.
See the individual user module data sheets for information on maximum frequencies for user modules.
August 5, 2008
Document No. 38-12013 Rev. *J
29
CYPRESS [ CYPRESS SEMICONDUCTOR ]
