1.
Pin Information
This chapter describes, lists, and illustrates the CY8C29x66 PSoC device pins and pinout configurations.
1.1
Pinouts
The CY8C29x66 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
1.1.1
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
28-Pin Part Pinout
Type
Table 1-1. 28-Pin Part Pinout (PDIP, SSOP, SOIC)
Digital
IO
IO
IO
IO
IO
IO
IO
IO
Power
IO
IO
IO
IO
Power
IO
IO
IO
IO
Input
IO
IO
IO
IO
IO
IO
IO
IO
Power
I
I
Analog
I
IO
IO
I
Pin
Name
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
SMP
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P1[0]
P1[2]
P1[4]
P1[6]
XRES
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Description
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
CY8C29466 28-Pin PSoC Device
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
P2[7]
P2[5]
A, I, P2[3]
A, I, P2[1]
SMP
I2CSCL,P1[7]
I2CSDA, P1[5]
P1[3]
I2CSCL,XTALin, P1[1]
Vss
I
I
Direct switched capacitor block input.
Direct switched capacitor block input.
Switch Mode Pump (SMP) connection to
external components required.
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
Crystal (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
Ground connection.
Crystal (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
Optional External Clock Input (EXTCLK).
Active high external reset with internal pull
down.
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND).
External Voltage Reference (VREF).
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PDIP
SSOP
SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6],ExternalVREF
P2[4],ExternalAGND
P2[2], A, I
P2[0], A, I
XRES
P1[6]
P1[4],EXTCLK
P1[2]
P1[0],XTALout,I2CSDA
I
IO
IO
I
LEGEND:
A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the
PSoC Mixed-Signal Array Technical Reference Manual
for details.
February 15, 2007
Document No. 38-12013 Rev. *H
8
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