CY8C29x66 Final Data Sheet
3. Electrical Specifications
3.4.7
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
≤
T
A
≤
85
°
C, or 3.0V to 3.6V and -40
°
C
≤
T
A
≤
85
°
C, respectively. Typical parameters apply to 5V and 3.3V at 25
°
C and
are for design guidance only.
Table 3-25: 5V AC External Clock Specifications
Symbol
F
OSCEXT
–
–
–
Frequency
High Period
Low Period
Power Up IMO to Switch
Description
Min
0.093
20.6
20.6
150
–
–
–
–
Typ
Max
24.6
5300
–
–
Units
MHz
ns
ns
µs
Notes
Table 3-26: 3.3V AC External Clock Specifications
Symbol
F
OSCEXT
Description
Frequency with CPU Clock divide by 1
Min
0.093
–
Typ
Max
12.3
Units
MHz
Notes
Maximum CPU frequency is 12 MHz at 3.3V.
With the CPU clock divider set to 1, the
external clock must adhere to the maximum
frequency and duty cycle requirements.
If the frequency of the external clock is
greater than 12 MHz, the CPU clock divider
must be set to 2 or greater. In this case, the
CPU clock divider will ensure that the fifty
percent duty cycle requirement is met.
F
OSCEXT
Frequency with CPU Clock divide by 2 or greater
0.186
–
24.6
MHz
–
–
–
High Period with CPU Clock divide by 1
Low Period with CPU Clock divide by 1
Power Up IMO to Switch
41.7
41.7
150
–
–
–
5300
–
–
ns
ns
µs
3.4.8
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
≤
T
A
≤
85
°
C, or 3.0V to 3.6V and -40
°
C
≤
T
A
≤
85
°
C, respectively. Typical parameters apply to 5V and 3.3V at 25
°
C and
are for design guidance only.
Table 3-27: AC Programming Specifications
Symbol
T
RSCLK
T
FSCLK
T
SSCLK
T
HSCLK
F
SCLK
T
ERASEB
T
WRITE
T
DSCLK
T
DSCLK3
Rise Time of SCLK
Fall Time of SCLK
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Description
1
1
40
40
0
–
–
–
–
Min
–
–
–
–
–
10
10
–
–
Typ
20
20
–
–
8
–
–
45
50
Max
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ns
Vdd
>
3.6
3.0
≤
Vdd
≤
3.6
Notes
February 15, 2007
Document No. 38-12013 Rev. *H
36