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CY8C29466-24PVXI 参数 Datasheet PDF下载

CY8C29466-24PVXI图片预览
型号: CY8C29466-24PVXI
PDF下载: 下载PDF文件 查看货源
内容描述: 的PSoC ™混合信号阵列 [PSoC㈢ Mixed-Signal Array]
分类和应用:
文件页数/大小: 48 页 / 656 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY8C29x66 Final Data Sheet
1. Pin Information
1.1.5
100-Pin Part Pinout (On-Chip Debug)
The 100-pin TQFP part is for the CY8C29000 On-Chip Debug (OCD) PSoC device.
Note
This part is only used for in-circuit debugging. It is NOT available for production
Table 1-6. 100-Pin Part Pinout (TQFP)
Analog
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Name
Description
No connection.
No connection.
Analog column mux input.
Pin
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Analog
Digital
Digital
Name
P1[6]
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
HCLK
CCLK
XRES
P4[0]
P4[2]
Vss
P4[4]
P4[6]
P2[0]
P2[2]
P2[4]
NC
P2[6]
NC
P0[0]
NC
NC
P0[2]
NC
P0[4]
NC
Description
NC
NC
IO I, M P0[1]
IO
M P2[7]
IO
M P2[5]
IO I, M P2[3]
IO I, M P2[1]
IO
M P4[7]
IO
M P4[5]
IO
M P4[3]
IO
M P4[1]
OCDE
OCDO
NC
Power Vss
IO
M P3[7]
IO
M P3[5]
IO
M P3[3]
IO
M P3[1]
IO
M P5[7]
IO
M P5[5]
IO
M P5[3]
IO
M P5[1]
IO
M P1[7]
NC
NC
NC
IO
P1[5]
IO
P1[3]
IO
P1[1]
NC
Vss
D+
D-
Vdd
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
NC
NC
NC
NC
P1[0]
P1[2]
P1[4]
Direct switched capacitor block input.
Direct switched capacitor block input.
IO
IO
IO
IO
IO
IO
IO
IO
IO
M
M
M
M
M
M
M
M
M
OCD even data IO.
OCD odd data output.
No connection.
Ground connection.
Input
IO
M
IO
M
Power
IO
M
IO
M
IO I, M
IO I, M
IO
IO
IO
I
OCD high-speed clock output.
OCD CPU clock output.
Active high pin reset with internal pull down.
Ground connection.
I2C Serial Clock (SCL).
No connection.
No connection.
No connection.
I2C Serial Data (SDA)
Crystal (XTALin), I2C Serial Clock (SCL),
ISSP SCLK*.
No connection.
Ground connection.
IO
IO
I, M
I, M
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND) input.
No connection.
External Voltage Reference (VREF) input.
No connection.
Analog column mux input.
No connection.
No connection.
Analog column mux input and column output.
No connection.
Analog column mux input and column output.
No connection.
Analog column mux input.
Supply voltage.
No connection.
Ground connection.
No connection.
No connection.
No connection.
No connection.
No connection.
No connection.
No connection.
No connection.
No connection.
No connection.
Analog column mux input.
No connection.
Analog column mux input and column output.
No connection.
Analog column mux input and column output.
No connection.
Power
USB
USB
Power
IO
IO
IO
IO
IO
IO
IO
IO
Supply voltage.
IO
IO
IO
No connection.
No connection.
No connection.
No connection.
Crystal (XTALout), I2C Serial Data (SDA),
ISSP SDATA*.
Optional External Clock Input (EXTCLK).
IO I, M P0[6]
Power
Vdd
NC
Power
Vss
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO I, M P0[7]
NC
IO IO, M P0[5]
NC
IO
IO, M P0[3]
NC
LEGEND
A = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input, OCD = On-Chip Debugger.
* These are the ISSP pins, which are not High Z at POR. See the
PSoC Mixed-Signal Array Technical Reference Manual
for details.
February 15, 2007
Document No. 38-12013 Rev. *H
14