CY8C27143, CY8C27243
CY8C27443, CY8C27543
CY8C27643
PSoC
®
Programmable System-on-Chip™
PSoC
®
Programmable System-on-Chip™
Features
■
Powerful Harvard-architecture processor
❐
M8C processor speeds up to 24 MHz
❐
8 × 8 multiply, 32-bit accumulate
❐
Low power at high speed
❐
Operating voltage: 3.0 V to 5.25 V
❐
Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
❐
Industrial temperature range: –40
C
to +85
C
Advanced peripherals (PSoC
®
blocks)
❐
Twelve rail-to-rail analog PSoC blocks provide:
• Up to 14-bit analog-to-digital converters (ADCs)
• Up to 9-bit digital-to-analog converters (DACs)
• Programmable gain amplifiers (PGAs)
• Programmable filters and comparators
❐
Eight digital PSoC blocks provide:
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
• Cyclical redundancy check (CRC) and pseudo random
sequence (PRS) modules
• Up to two full-duplex universal asynchronous receiver
transmitters (UARTs)
• Multiple serial peripheral interface (SPI)masters or slaves
• Connectable to all general-purpose I/O (GPIO) pins
❐
Complex peripherals by combining blocks
Precision, programmable clocking
❐
Internal 2.5% 24- / 48-MHz main oscillator
❐
24- / 48-MHz with optional 32 kHz crystal
❐
Optional external oscillator up to 24 MHz
❐
Internal oscillator for watchdog and sleep
Flexible on-chip memory
❐
16 KB flash program storage 50,000 erase/write cycles
❐
256-bytes SRAM data storage
❐
In-system serial programming (ISSP)
❐
Partial flash updates
❐
Flexible protection modes
❐
Electronically erasable programmable read only memory
(EEPROM) emulation in flash
Programmable pin configurations
❐
25-mA sink, 10-mA source on all GPIOs
❐
Pull-up, pull-down, high-Z, strong, or open-drain drive modes
on all GPIOs
❐
Eight standard analog inputs on GPIO, plus four additional
analog inputs with restricted routing
❐
Four 30-mA analog outputs on GPIOs
❐
Configurable interrupt on all GPIOs
■
Additional system resources
2
❐
I C slave, master, and multi-master to 400 kHz
❐
Watchdog and sleep timers
❐
User-configurable low-voltage detection (LVD)
❐
Integrated supervisory circuit
❐
On-chip precision voltage reference
Complete development tools
❐
Free development software (PSoC Designer™)
❐
Full-featured, in-circuit emulator (ICE) and programmer
❐
Full-speed emulation
❐
Complex breakpoint structure
❐
128 KB trace memory
■
■
Logic Block Diagram
PSoC
CORE
System Bus
Global Digital Interconnect
SRAM
256 Bytes
Interrupt
Controller
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Analog
Drivers
Global Analog Interconnect
Flash 16 KB
Sleep and
Watchdog
■
SROM
CPU Core (M8C)
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
■
DIGITAL SYSTEM
Digital
Block
Array
ANALOG SYSTEM
Analog
Block
Array
Analog
Ref.
Analog
Input
Muxing
■
Digital
Clocks
Multiply
Accum.
POR and LVD
Decimator
I
2
C
System Resets
Internal
Voltage
Ref.
Switch
Mode
Pump
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 38-12012 Rev. *X
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 9, 2013