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CY8C24223A-24PVXI 参数 Datasheet PDF下载

CY8C24223A-24PVXI图片预览
型号: CY8C24223A-24PVXI
PDF下载: 下载PDF文件 查看货源
内容描述: PSoC混合信号阵列 [PSoC Mixed-Signal Array]
分类和应用:
文件页数/大小: 47 页 / 499 K
品牌: CYPRESS [ CYPRESS ]
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CY8C24x23A Final Data Sheet  
PSoC™ Overview  
processor. The CPU utilizes an interrupt controller with 11 vec-  
tors, to simplify programming of real time embedded events.  
Program execution is timed and protected using the included  
Sleep and Watch Dog Timers (WDT).  
Digital peripheral configurations include those listed below.  
PWMs (8 to 32 bit)  
PWMs with Dead band (8 to 24 bit)  
Counters (8 to 32 bit)  
Memory encompasses 4 KB of Flash for program storage, 256  
bytes of SRAM for data storage, and up to 2 KB of EEPROM  
emulated using the Flash. Program Flash utilizes four protec-  
tion levels on blocks of 64 bytes, allowing customized software  
IP protection.  
Timers (8 to 32 bit)  
UART 8 bit with selectable parity  
SPI master and slave  
I2C slave and multi-master (1 available as a System  
Resource)  
The PSoC device incorporates flexible internal clock genera-  
tors, including a 24 MHz IMO (internal main oscillator) accurate  
to 2.5% over temperature and voltage. The 24 MHz IMO can  
also be doubled to 48 MHz for use by the digital system. A low  
power 32 kHz ILO (internal low speed oscillator) is provided for  
the Sleep timer and WDT. If crystal accuracy is desired, the  
ECO (32.768 kHz external crystal oscillator) is available for use  
as a Real Time Clock (RTC) and can optionally generate a crys-  
tal-accurate 24 MHz system clock using a PLL. The clocks,  
together with programmable clock dividers (as a System  
Resource), provide the flexibility to integrate almost any timing  
requirement into the PSoC device.  
Cyclical Redundancy Checker/Generator (8 to 32 bit)  
IrDA (up to 1)  
Pseudo Random Sequence Generators (8 to 32 bit)  
The digital blocks can be connected to any GPIO through a  
series of global buses that can route any signal to any pin. The  
buses also allow for signal multiplexing and for performing logic  
operations. This configurability frees your designs from the con-  
straints of a fixed peripheral controller.  
Digital blocks are provided in rows of four, where the number of  
blocks varies by PSoC device family. This allows you the opti-  
mum choice of system resources for your application. Family  
resources are shown in the table titled “PSoC Device Charac-  
teristics” on page 3.  
PSoC GPIOs provide connection to the CPU, digital and analog  
resources of the device. Each pin’s drive mode may be selected  
from eight options, allowing great flexibility in external interfac-  
ing. Every pin also has the capability to generate a system inter-  
rupt on high level, low level, and change from last read.  
The Analog System  
The Analog System is composed of 6 configurable blocks, each  
comprised of an opamp circuit allowing the creation of complex  
analog signal flows. Analog peripherals are very flexible and  
can be customized to support specific application requirements.  
Some of the more common PSoC analog functions (most avail-  
able as user modules) are listed below.  
The Digital System  
The Digital System is composed of 4 digital PSoC blocks. Each  
block is an 8-bit resource that can be used alone or combined  
with other blocks to form 8, 16, 24, and 32-bit peripherals, which  
are called user module references.  
Analog-to-digital converters (up to 2, with 6- to 14-bit resolu-  
Port 1  
tion, selectable as Incremental, Delta Sigma, and SAR)  
Port 2  
Port 0  
Filters (2 and 4 pole band-pass, low-pass, and notch)  
Amplifiers (up to 2, with selectable gain to 48x)  
Instrumentation amplifiers (1 with selectable gain to 93x)  
Comparators (up to 2, with 16 selectable thresholds)  
DACs (up to 2, with 6- to 9-bit resolution)  
To System Bus  
Digital Clocks  
From Core  
To Analog  
System  
DIGITAL SYSTEM  
Digital PSoC Block Array  
Multiplying DACs (up to 2, with 6- to 9-bit resolution)  
High current output drivers (two with 30 mA drive as a Core  
Row 0  
8
4
8
Resource)  
8
8
DBB00  
DBB01  
DCB02  
DCB03  
1.3V reference (as a System Resource)  
DTMF dialer  
4
Modulators  
Correlators  
GIE[7:0]  
GIO[7:0]  
GOE[7:0]  
GOO[7:0]  
Global Digital  
Interconnect  
Peak detectors  
Many other topologies possible  
Digital System Block Diagram  
September 8, 2004  
Document No. 38-12028 Rev. *B  
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