CY8C24x23A Final Data Sheet
1. Pin Information
1.1.4
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
32-Pin Part Pinout
Type
Table 1-4. 32-Pin Part Pinout (QFN**)
Digital
IO
IO
IO
IO
Power
Power
I
I
Analog
Pin
Name
P2[7]
P2[5]
P2[3]
P2[1]
Vss
SMP
P1[7]
P1[5]
NC
P1[3]
P1[1]
Description
CY8C24423A 32-Pin PSoC Device
P0[1], A, I
P0[3], A, IO
P0[5], A, IO
P0[7], A, I
Vdd
P0[6], A, I
P2[7]
P2[5]
A, I, P2[3]
A, I, P2[1]
Vss
SMP
I2CSCL, P1[7]
I2CSDA, P1[5]
1
2
3
4
5
6
7
8
P0[4], A, I
NC
24
23
22
21
20
19
18
17
P0[2], A, I
P0[0], A, I
P2[6],External VRef
P2[4],External AGND
P2[2], A, I
P2[0], A, I
XRES
P1[6]
Direct switched capacitor block input.
Direct switched capacitor block input.
Switch Mode Pump (SMP) connection to
external components required.
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
No connection.
Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*.
Ground connection.
Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*.
Optional External Clock Input (EXTCLK).
No connection.
Active high external reset with internal pull
down.
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND).
External Voltage Reference (VRef).
Analog column mux input.
Analog column mux input.
No connection.
Analog column mux input.
Analog column mux input.
Supply voltage.
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Ground connection.
P1[0]
P1[2]
P1[4]
NC
P1[6]
Input
I
I
XRES
P2[0]
P2[2]
P2[4]
P2[6]
I
I
I
I
Power
I
IO
IO
I
P0[0]
P0[2]
NC
P0[4]
P0[6]
Vdd
P0[7]
P0[5]
P0[3]
P0[1]
LEGEND:
A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the
PSoC Mixed-Signal Array Technical Reference Manual
for details.
** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
should be electrically floated and not connected to any other signal.
October 17, 2006
Document No. 38-12028 Rev. *F
NC
P1[3]
Power
Vss
9
10
I2CSCL,XTALin,P1[1] 11
Vss 12
I2CSDA,XTALout,P1[0] 13
P1[2] 14
EXTCLK,P1[4] 15
NC 16
32
31
30
29
28
27
26
25
QFN
(Top View )
11
CYPRESS [ CYPRESS SEMICONDUCTOR ]
