CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet
1. Pin Information
1.6
100-Ball VFBGA Part Pinout (On-Chip Debug)
The 100-pin VFBGA part table and drawing below is for the CY8C24094 On-Chip Debug (OCD) PSoC device.
Note
This part is only used for in-circuit debugging. It is NOT available for production.
Table 1-6. 100-Ball Part Pinout (VFBGA)
Analog
Pin
No.
Name
Description
Pin
No.
Analog
Digital
Digital
Name
Description
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
Vss
Vss
NC
NC
NC
Power
Vdd
NC
NC
Power
Vss
Power
Vss
Power
Vss
Power
Vss
IO
I,M P2[1]
IO
I,M P0[1]
IO
I,M P0[7]
Power
Vdd
IO
I,M P0[2]
IO
I,M P2[2]
Power
Vss
Power
Vss
NC
IO
M P4[1]
IO
M P4[7]
IO
M P2[7]
IO IO,M P0[5]
IO
I,M P0[6]
IO
I,M P0[0]
IO
I,M P2[0]
IO
M P4[2]
NC
NC
IO
M P3[7]
IO
M P4[5]
IO
M P2[5]
IO IO,M P0[3]
IO
I,M P0[4]
IO
M P2[6]
IO
M P4[6]
IO
M P4[0]
CCLK
NC
NC
IO
M P4[3]
IO
I,M P2[3]
Power
Vss
Power
Vss
IO
M P2[4]
IO
M P4[4]
IO
M P3[6]
HCLK
Power
Power
Ground connection.
Ground connection.
No connection.
No connection.
No connection.
Supply voltage.
No connection.
No connection.
Ground connection.
Ground connection.
Ground connection.
Ground connection.
Direct switched capacitor block input.
Analog column mux input.
Analog column mux input.
Supply voltage.
Analog column mux input.
Direct switched capacitor block input.
Ground connection.
Ground connection.
No connection.
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
H1
H2
H3
H4
Analog column mux input and column output. H5
Analog column mux input.
H6
Analog column mux input.
H7
Direct switched capacitor block input.
H8
H9
No connection.
H10
No connection.
J1
J2
J3
J4
Analog column mux input and column output. J5
Analog column mux input.
J6
External Voltage Reference (VREF) input.
J7
J8
J9
OCD CPU clock output.
J10
No connection.
K1
No connection.
K2
K3
Direct switched capacitor block input.
K4
Ground connection.
K5
Ground connection.
K6
External Analog Ground (AGND) input.
K7
K8
K9
OCD high-speed clock output.
K10
IO
M
IO
M
IO
M
Power
Power
IO
M
IO
M
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
M
M
M
M
M
M
M
M
IO
M
IO
M
IO
M
IO
M
IO
M
IO
M
IO
M
IO
M
IO
Power
Power
USB
USB
Power
IO
IO
IO
M
Power
Power
Power
Power
Power
IO
IO
IO
Power
Power
OCDE
P5[7]
P3[5]
P5[1]
Vss
Vss
P5[0]
P3[0]
XRES
P7[1]
OCDO
P5[5]
P3[3]
P1[7]
P1[1]
P1[0]
P1[6]
P3[4]
P5[6]
P7[2]
NC
P5[3]
P3[1]
P1[5]
P1[3]
P1[2]
P1[4]
P3[2]
P5[4]
P7[3]
Vss
Vss
D+
D-
Vdd
P7[7]
P7[0]
P5[2]
Vss
Vss
Vss
Vss
NC
NC
Vdd
P7[6]
P7[5]
P7[4]
Vss
Vss
OCD even data IO.
Ground connection.
Ground connection.
Active high pin reset with internal pull down.
OCD odd data output.
I2C Serial Clock (SCL).
I2C Serial Clock (SCL), ISSP SCLK*.
I2C Serial Data (SDA), ISSP SDATA*.
No connection.
I2C Serial Data (SDA).
Ground connection.
Ground connection.
Supply voltage.
Ground connection.
Ground connection.
Ground connection.
Ground connection.
No connection.
No connection.
Supply voltage.
Ground connection.
Ground connection.
LEGEND
A = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection, OCD = On-Chip Debugger.
* This is the ISSP pin, which is not High Z at POR. See the
PSoC Mixed-Signal Array Technical Reference Manual
for details.
February 15, 2007
Document No. 38-12018 Rev. *J
15
CYPRESS [ CYPRESS SEMICONDUCTOR ]
