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CY8C24794-24LFXI 参数 Datasheet PDF下载

CY8C24794-24LFXI图片预览
型号: CY8C24794-24LFXI
PDF下载: 下载PDF文件 查看货源
内容描述: 的PSoC ™混合信号阵列 [PSoC㈢ Mixed-Signal Array]
分类和应用:
文件页数/大小: 48 页 / 648 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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PSoC® Mixed-Signal Array
CY8C24094, CY8C24794,
CY8C24894, and CY8C24994
Features
Final Data Sheet
CY8C24894 includes an XRES pin to support In-System Serial Programming (ISSP) and external reset control
Powerful Harvard Architecture Processor
M8C Processor Speeds to 24 MHz
Two 8x8 Multiply, 32-Bit Accumulate
Low Power at High Speed
3.0 to 5.25V Operating Voltage
Industrial Temperature Range: -40°C to +85°C
USB Temperature Range: -10°C to +85°C
Advanced Peripherals (PSoC Blocks)
6 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
4 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Full-Duplex UART
- Multiple SPI™ Masters or Slaves
- Connectable to all GPIO Pins
Complex Peripherals by Combining Blocks
Capacitive Sensing Application Capability
Full-Speed USB (12 Mbps)
Four Uni-Directional Endpoints
One Bi-Directional Control Endpoint
USB 2.0 Compliant
Dedicated 256 Byte Buffer
No External Crystal Required
Flexible On-Chip Memory
16K Flash Program Storage 50,000 Erase/
Write Cycles
1K SRAM Data Storage
In-System Serial Programming (ISSP)
Partial Flash Updates
Flexible Protection Modes
EEPROM Emulation in Flash
Programmable Pin Configurations
25 mA Sink on all GPIO
Pull up, Pull down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
Up to 48 Analog Inputs on GPIO
Two 33 mA Analog Outputs on GPIO
Configurable Interrupt on all GPIO
Precision, Programmable Clocking
Internal ±4% 24/48 MHz Oscillator
Internal Oscillator for Watchdog and Sleep
.25% Accuracy for USB with no External
Components
Additional System Resources
I
2
C™ Slave, Master, and Multi-Master to
400 kHz
Watchdog and Sleep Timers
User-Configurable Low Voltage Detection
Integrated Supervisory Circuit
On-Chip Precision Voltage Reference
Complete Development Tools
Free Development Software
(PSoC Designer™)
Full-Featured, In-Circuit Emulator and
Programmer
Full Speed Emulation
Complex Breakpoint Structure
128K Bytes Trace Memory
Port 7
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Analog
Drivers
PSoC® Functional Overview
The PSoC® family consists of many
Mixed-Signal Array with
On-Chip Controller
devices. All PSoC family devices are
designed to replace traditional MCUs, system ICs, and the
numerous discrete components that surround them. The PSoC
CY8C24x94 devices are unique members of the PSoC family
because it includes a full-featured, full-speed (12 Mbps) USB
port. Configurable analog, digital, and interconnect circuitry
enable a high level of integration in a host of industrial, con-
sumer, and communication applications.
This architecture allows the user to create customized periph-
eral configurations that match the requirements of each individ-
ual application. Additionally, a fast CPU, Flash program
memory, SRAM data memory, and configurable IO are included
in a range of convenient pinouts and packages.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources including a full-speed USB port. Config-
urable global busing allows all the device resources to be com-
bined into a complete custom system. The PSoC CY8C24x94
devices can have up to seven IO ports that connect to the glo-
bal digital and analog interconnects, providing access to 4 digi-
tal blocks and 6 analog blocks.
System Bus
Global Digital Interconnect
Global Analog Interconnect
PSoC CORE
SRAM
1K
Interrupt
Controller
SROM
Flash 16K
Sleep and
Watchdog
CPU Core (M8C)
ClockSources
(Includes IMO and ILO)
DIGITAL SYSTEM
Digital
Block
Array
ANALOG SYSTEM
Analog
Ref.
Analog
Block
Array
Digital
2
Decimator
Clocks MACs Type 2
I2C
Internal
POR and LVD
Voltage
System Resets
Ref.
USB
Analog
Input
Muxing
SYSTEM RESOURCES
February 15, 2007
© Cypress Semiconductor 2004-2007 — Document No. 38-12018 Rev. *J
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