CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
15. Document History Page
Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB FX2LP™ USB Microcontroller High
Speed USB Peripheral Controller
Document Number: 38-08032
Orig. of Submission
Rev. ECN No.
Description of Change
Change
Date
**
124316
VCS
03/17/03 New data sheet
*A 128461
VCS
09/02/03 Added PN CY7C68015A throughout data sheet
Modified Figure 1 to add ECC block and fix errors
Removed word “compatible” where associated with I2C
Corrected grammar and formatting in various locations
Updated Sections 3.2.1, 3.9, 3.11, Table 9, Section 5.0
Added Sections 3.15, 3.18.4, 3.20
Modified Figure 5 for clarity
Updated Figure 36 to match current spec revision
*B 130335
*C 131673
KKV
KKU
10/09/03 Restored PRELIMINARY to header (had been removed in error from rev. *A)
02/12/04 Section 8.1 changed “certified” to “compliant”
Table 14 added parameter VIH_X and VIL_X
Added Sequence diagrams Section 9.16
Updated Ordering information with lead-free parts
Updated Registry Summary
Section 3.12.4:example changed to column 8 from column 9
Updated Figure 14 memory write timing Diagram
Updated section 3.9 (reset)
Updated section 3.15 ECC Generation
*D 230713
*E 242398
KKU
TMD
MON
See ECN Changed Lead free Marketing part numbers in Table 33 as per spec change in 28-00054.
See ECN Minor Change: data sheet posted to the web,
*F
*G
*H
271169
See ECN Added USB-IF Test ID number
Added USB 2.0 logo
Added values for Isusp, Icc, Power Dissipation, Vih_x, Vil_x
Changed VCC from + 10% to + 5%
Changed PKTEND to FLAGS output propagation delay (asynchronous interface) in
Table 28 from a max value of 70 ns to 115 ns
316313 MON
338901 MON
See ECN Removed CY7C68013A-56PVXCT part availability
Added parts ideal for battery powered applications: CY7C68014A, CY7C68016A
Provided additional timing restrictions and requirement about the use of PKETEND pin to
commit a short one byte/word packet subsequent to committing a packet automatically
(when in auto mode).
Added Min Vcc Ramp Up time (0 to 3.3v)
See ECN Added information about the AUTOPTR1/AUTOPTR2 address timing with regards to data
memory read/write timing diagram.
Removed TBD for Min value of Clock to FIFO Data Output Propagation Delay (tXFD) for
Slave FIFO Synchronous Read
Changed Table 33 to include part CY7C68016A-56LFXC in the part listed for battery
powered applications
Added register GPCR2 in register summary
*I
371097 MON
See ECN Added timing for strobing RD#/WR# signals when using PortC strobe feature (Section 10.5)
*J
397239
MON
See ECN Removed XTALINSRC register from register summary.
Changed Vcc margins to +10%
Added 56-pin VFBGA Pin Package Diagram
Added 56-pin VFBGA definition in pin listing
Added RDK part number to the Ordering Information table
Document #: 38-08032 Rev. *N
Page 61 of 62
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