CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
10.15 Slave FIFO Synchronous Address
Figure 27. Slave FIFO Synchronous Address Timing Diagram[20]
IFCLK
SLCS/FIFOADR [1:0]
t
t
FAH
SFA
Table 31. Slave FIFO Synchronous Address Parameters [21]
Parameter
tIFCLK
tSFA
tFAH
Description
Interface Clock Period
Min
20.83
25
Max
Unit
ns
200
FIFOADR[1:0] to Clock Setup Time
Clock to FIFOADR[1:0] Hold Time
ns
10
ns
10.16 Slave FIFO Asynchronous Address
Figure 28. Slave FIFO Asynchronous Address Timing Diagram[20]
SLCS/FIFOADR [1:0]
t
FAH
t
SFA
SLRD/SLWR/PKTEND
Table 32. Slave FIFO Asynchronous Address Parameters[23]
Parameter
Description
Min
10
Max
Unit
ns
tSFA
tFAH
FIFOADR[1:0] to SLRD/SLWR/PKTEND Setup Time
RD/WR/PKTEND to FIFOADR[1:0] Hold Time
10
ns
Document #: 38-08032 Rev. *N
Page 49 of 62
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