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CY7C68014A-56LTXC 参数 Datasheet PDF下载

CY7C68014A-56LTXC图片预览
型号: CY7C68014A-56LTXC
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内容描述: EZ- USB FX2LP USB微控制器,高速USB外设控制器 [EZ-USB FX2LP USB Microcontroller High Speed USB Peripheral Controller]
分类和应用: 总线控制器微控制器和处理器外围集成电路数据传输PC可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 62 页 / 1626 K
品牌: CYPRESS [ CYPRESS ]
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CY7C68013A, CY7C68014A  
CY7C68015A, CY7C68016A  
Figure 40. 56 VFBGA (5 x 5 x 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56 (001-03901)  
TOP VIEW  
BOTTOM VIEW  
Ø0.05 M C  
Ø0.15 M C A B  
Ø0.30 0.05(56X)  
A1 CORNER  
PIN A1 CORNER  
1
2
3
4
5
6
6
8
8
7
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
F
F
G
H
G
H
0.50  
3.50  
-B-  
-A-  
5.00 0.10  
SIDE VIEW  
5.00 0.10  
0.10(4X)  
REFERENCE JEDEC: MO-195C  
PACKAGE WEIGHT: 0.02 grams  
-C-  
SEATING PLANE  
001-03901-*B  
13. PCB Layout Recommendations  
Follow these recommendations to ensure reliable high  
performance operation:[24]  
Bypass and flyback caps on VBus, near connector, are  
recommended.  
Four layer impedance controlled boards are required to  
maintain signal quality.  
DPLUS and DMINUS trace lengths should be kept to within 2  
mm of each other in length, with preferred length of 20 to  
30 mm.  
Specify impedance targets (ask your board vendor what they  
can achieve).  
Maintain a solid ground plane under the DPLUS and DMINUS  
traces. Do not allow the plane to split under these traces.  
To control impedance, maintain trace widths and trace spacing.  
Minimize stubs to minimize reflected signals.  
Do not place vias on the DPLUS or DMINUS trace routing.  
Isolate the DPLUS and DMINUS traces from all other signal  
traces by no less than 10 mm.  
Connections between the USB connector shell and signal  
ground must be near the USB connector.  
Note  
24. Source for recommendations: EZ-USB FX2™PCB Design Recommendations, http://www.cypress.com and High Speed USB Platform Design Guidelines,  
http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.  
Document #: 38-08032 Rev. *N  
Page 59 of 62  
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