CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
10.4 Data Memory Write
Figure 14. Data Memory Write Timing Diagram
t
CL
CLKOUT
A[15..0]
t
AV
t
t
t
STBL
STBH
AV
WR#
CS#
t
SCSL
t
ON1
t
OFF1
data out
D[7..0]
Stretch = 1
t
CL
CLKOUT
A[15..0]
t
AV
WR#
CS#
t
ON1
t
OFF1
data out
D[7..0]
Table 17. Data Memory Write Parameters
Parameter Description
Delay from Clock to Valid Address
Min
0
Max
10.7
11.2
11.2
13.0
13.1
13.1
Unit
ns
Notes
tAV
tSTBL
tSTBH
tSCSL
tON1
Clock to WR Pulse LOW
Clock to WR Pulse HIGH
Clock to CS Pulse LOW
Clock to Data Turn-on
Clock to Data Hold Time
0
ns
0
ns
ns
0
0
ns
tOFF1
ns
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either RD#
or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the address valid time for which is based on
the stretch value.
Document #: 38-08032 Rev. *N
Page 40 of 62
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