CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 11. FX2LP Pin Descriptions (continued)
128 100 56 56 56
Name
Type Default
Description
TQFP TQFP SSOP QFN VFBGA
112
90
PE4 or
RXD1OUT
I/O/Z
I
Multiplexed pin whose function is selected by the
(PE4) PORTECFG.4 bit.
PE4 is a bidirectional I/O port pin.
RXD1OUT is an active-HIGH output from 8051 UART1.
When RXD1OUT is selected and UART1 is in Mode 0,
this pin provides the output data for UART1 only when
it is in sync mode. In Modes 1, 2, and 3, this pin is HIGH.
113
114
91
92
PE5 or
INT6
I/O/Z
I/O/Z
I
Multiplexed pin whose function is selected by the
(PE5) PORTECFG.5 bit.
PE5 is a bidirectional I/O port pin.
INT6 isthe8051INT6interruptrequestinputsignal. The
INT6 pin is edge-sensitive, active HIGH.
PE6 or
T2EX
I
Multiplexed pin whose function is selected by the
(PE6) PORTECFG.6 bit.
PE6 is a bidirectional I/O port pin.
T2EX is an active-HIGH input signal to the 8051 Timer2.
T2EX reloads timer 2 on its falling edge. T2EX is active
only if the EXEN2 bit is set in T2CON.
115
4
93
3
PE7 or
GPIFADR8
I/O/Z
Input
I
Multiplexed pin whose function is selected by the
(PE7) PORTECFG.7 bit.
PE7 is a bidirectional I/O port pin.
GPIFADR8 is a GPIF address output pin.
8
9
1
2
1A
1B
RDY0 or
SLRD
N/A Multiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
RDY0 is a GPIF input signal.
SLRD is the input-only read strobe with programmable
polarity (FIFOPINPOLAR.3) for the slave FIFOs
connected to FD[7..0] or FD[15..0].
5
4
RDY1 or
SLWR
Input
N/A Multiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
RDY1 is a GPIF input signal.
SLWR is the input-only write strobe with programmable
polarity (FIFOPINPOLAR.2) for the slave FIFOs
connected to FD[7..0] or FD[15..0].
6
7
5
6
RDY2
RDY3
RDY4
RDY5
Input
Input
Input
Input
O/Z
N/A RDY2 is a GPIF input signal.
N/A RDY3 is a GPIF input signal.
N/A RDY4 is a GPIF input signal.
N/A RDY5 is a GPIF input signal.
8
7
9
8
69
54
36
29
7H
CTL0 or
FLAGA
H
Multiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
CTL0 is a GPIF control output.
FLAGA is a programmable slave-FIFO output status
flag signal.
Defaults to programmable for the FIFO selected by the
FIFOADR[1:0] pins.
Document #: 38-08032 Rev. *N
Page 26 of 62
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