欢迎访问ic37.com |
会员登录 免费注册
发布采购

CY7C68013A-100AXI 参数 Datasheet PDF下载

CY7C68013A-100AXI图片预览
型号: CY7C68013A-100AXI
PDF下载: 下载PDF文件 查看货源
内容描述: EZ- USB FX2LP ™ USB微控制器,高速USB外设控制器 [EZ-USB FX2LP? USB Microcontroller High Speed USB Peripheral Controller]
分类和应用: 总线控制器微控制器和处理器外围集成电路数据传输可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 62 页 / 1809 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
更多
  •  
  • 供货商
  • 型号*
  • 数量*
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
批量询价选中的记录已选中0条,每次最多15条。
 浏览型号CY7C68013A-100AXI的Datasheet PDF文件第2页浏览型号CY7C68013A-100AXI的Datasheet PDF文件第3页浏览型号CY7C68013A-100AXI的Datasheet PDF文件第4页浏览型号CY7C68013A-100AXI的Datasheet PDF文件第5页浏览型号CY7C68013A-100AXI的Datasheet PDF文件第6页浏览型号CY7C68013A-100AXI的Datasheet PDF文件第7页浏览型号CY7C68013A-100AXI的Datasheet PDF文件第8页浏览型号CY7C68013A-100AXI的Datasheet PDF文件第9页 
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
EZ-USB FX2LP™ USB Microcontroller
High Speed USB Peripheral Controller
1. Features (CY7C68013A/14A/15A/16A)
USB 2.0 USB IF High Speed Certified (TID # 40460272)
Single Chip Integrated USB 2.0 Transceiver, Smart SIE, and
Enhanced 8051 Microprocessor
Fit, Form, and Function Compatible with the FX2
Pin compatible
Object-code-compatible
Functionally Compatible (FX2LP is a superset)
Ultra Low Power: I
CC
No More than 85 mA in any Mode
Ideal for bus and battery powered applications
Software: 8051 Code Runs from:
Internal RAM, which is downloaded through USB
Internal RAM, which is loaded from EEPROM
External memory device (128 pin package)
16 KBytes of On-Chip Code/Data RAM
Four Programmable BULK/INTERRUPT/ISOCHRONOUS
Endpoints
Buffering options: double, triple, and quad
Additional Programmable (BULK/INTERRUPT) 64 Byte
Endpoint
8-bit or 16-bit External Data Interface
Smart Media Standard ECC Generation
GPIF (General Programmable Interface)
Enables direct connection to most parallel interfaces
Programmable waveform descriptors and configuration
registers to define waveforms
Supports multiple Ready (RDY) inputs and Control (CTL)
outputs
Integrated, Industry Standard Enhanced 8051
48 MHz, 24 MHz, or 12 MHz CPU operation
Four clocks per instruction cycle
Two USARTS
Three counter/timers
Expanded interrupt system
Two data pointers
3.3V Operation with 5V Tolerant Inputs
Vectored USB Interrupts and GPIF/FIFO Interrupts
Separate Data Buffers for the Setup and Data Portions of a
CONTROL Transfer
Integrated I
2
C Controller, Runs at 100 or 400 kHz
Four Integrated FIFOs
Integrated glue logic and FIFOs lower system cost
Automatic conversion to and from 16-bit buses
Master or slave operation
Uses external clock or asynchronous strobes
Easy interface to ASIC and DSP ICs
Available in Commercial and Industrial Temperature Grade
(all packages except VFBGA)
Cypress Semiconductor Corporation
Document #: 38-08032 Rev. *M
198 Champion Court
San Jose
,
CA 95134-1709
• 408-943-2600
Revised May 22, 2009