CY7C68300B/CY7C68301B
CY7C68320/CY7C68321
5.2
Pin Descriptions
between the 68300B/01B and 68320/321 pinouts for the 56-
pin packages. For information on the CY7C68300A pinout,
please refer to the CY7C68300A data sheet that is found in the
“EZ-USB AT2” folder of the CY4615B reference design kit CD.
The following table lists the pinouts for the 56-pin SSOP, 56-
pin QFN and 100-pin TQFP package options for the AT2LP.
Please refer to the Pin Diagrams in section 5.1 for differences
Table 5-1. AT2LP Pin Descriptions
Note: (Italics pin names denote pin functionality during CY7C68300A-compatibility mode)
56
SSOP
1
2
3
4
5
56
QFN
50
51
52
53
54
[3]
100
TQFP
96
97
98
99
100
[3]
Pin Name
DD13
DD14
DD15
GND
ATAPUEN
(NC)
Pin Default State
Type at Start-up
Pin Description
[1]
I/O
Hi-Z
ATA Data bit 13.
I/O
[1]
I/O
[1]
GND
I/O
Hi-Z
Hi-Z
ATA Data bit 14.
ATA Data bit 15.
Ground.
ATA pull-up voltage source for bus-powered applica-
tions (see section 5.3.10).
Alternate Function:
Input when the EEPROM config-
uration byte 8 has bit 7 set to one. The input value is
reported through EP1IN (byte 0, bit 2).
V
CC
. Connect to 3.3V power source.
Input
Input
Ground.
ATA Control.
ATA Control.
Ground.
6
7
8
9
N/A
55
56
1
2
N/A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
[3]
V
CC
GND
IORDY
DMARQ
GND
PWR
GND
I
[1]
I
[1]
10
11
12
13
N/A
3
4
5
6
N/A
AV
CC
XTALOUT
XTALIN
AGND
NC
PWR
Xtal
Xtal
GND
Xtal
Xtal
Analog V
CC
. Connect to V
CC
through the shortest path
possible.
24-MHz Crystal Output
(see section 5.3.3).
24-MHz Crystal Input
(see section 5.3.3).
Analog Ground.
Connect to ground with as short a
path as possible.
No Connect.
14
15
16
17
18
19
N/A
N/A
7
8
9
10
11
12
N/A
N/A
V
CC
DPLUS
DMINUS
GND
V
CC
GND
SYSIRQ
GND
PWR
I/O
I/O
GND
PWR
GND
I
GND
Hi-Z
Hi-Z
V
CC
. Connect to 3.3V power source.
USB D+ Signal
(see section 5.3.1).
USB D– Signal
(see section 5.3.1).
Ground.
V
CC
. Connect to 3.3V power source.
Ground.
Input
Active HIGH.
USB interrupt request (see section
5.3.4). Tie to GND if functionality is not used.
Ground.
20
13
[3]
PWR500#
[2]
(PU
10K)
GND (RESERVED)
I/O
Active LOW.
VBUS power granted indicator used in
bus-powered designs (see section 5.3.11).
Alternate Function
for 68320.
Reserved.
Tie to GND.
21
14
27
Notes:
1. If byte 8, bit 4 of the EEPROM is set to ‘0’, the ATA interface pins are only active when VBUS_ATA_EN is asserted. See section 5.3.9.
2. A ‘#’ sign after the pin name indicates that it is active LOW.
3. The General Purpose inputs can be enabled on ATAPUEN, PWR500#, and DRVPWRVLD via EEPROM byte 8, bit 7 on CY7C68320/CY7C68321.
Document 38-08033 Rev. *D
Page 7 of 36
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