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CY7C68300B-56PVXC 参数 Datasheet PDF下载

CY7C68300B-56PVXC图片预览
型号: CY7C68300B-56PVXC
PDF下载: 下载PDF文件 查看货源
内容描述: EZ- USB AT2LPTM USB 2.0到ATA / ATAPI桥 [EZ-USB AT2LPTM USB 2.0 to ATA/ATAPI Bridge]
分类和应用:
文件页数/大小: 36 页 / 457 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7C68300B/CY7C68301B
CY7C68320/CY7C68321
EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge
1.0
Features (CY7C68300B/CY7C68301B and
CY7C68320/CY7C68321)
• Support for CompactFlash and one ATA/ATAPI device
• Can place the ATA interface in high-impedance (Hi-Z) to
allow sharing of the ATA bus with another controller (e.g.,
an IEEE-1394 to ATA bridge chip or MP3 Decoder)
• Support for board-level manufacturing test via USB
interface
• Low-power 3.3V operation
• Fully compatible with native USB mass storage class drivers
• Cypress mass storage class drivers available for Windows
(98SE, ME, 2000, XP) and Mac OS X
• Fixed-function mass storage device—requires no firmware
code
• Two power modes: Self-powered and USB bus-powered to
enable bus powered CF readers and truly portable USB
hard drives
• Certified compliant for USB 2.0 (TID# 40460273), the USB
Mass Storage Class, and the USB Mass Storage Class
Bulk-Only Transport (BOT) Specification
• Operates at high (480-Mbps) or full (12-Mbps) speed USB
• Complies with ATA/ATAPI-6 specification
• Supports 48-bit addressing for large hard drives
• Supports ATA security features
• Supports all ATA commands via ATACB function
• Supports mode page 5 for BIOS boot support
• Supports ATAPI serial number VPD page retrieval for Digital
Rights Management (DRM) compatibility
• Supports PIO modes 0, 3, 4, multiword DMA mode 2, and
UDMA modes 2, 3, 4
• Uses one external serial EEPROM for storage of USB
descriptors and device configuration data
• ATA interface IRQ signal support
• Support for one or two ATA/ATAPI devices
1.1
Features (CY7C68320/CY7C68321 only)
• Supports HID interface or custom GPIOs to enable features
such as single button backup, power-off, LED-based notifi-
cation, etc.
• Lead-free 56-pin QFN and 100-pin TQFP packages
• CY7C68321 is ideal for battery-powered designs
• CY7C68320 is ideal for self- and bus-powered designs
1.2
Features (CY7C68300B/CY7C68301B only)
• Pin-compatible with CY7C68300A (using Backward
Compatibility mode)
• Lead-free 56-pin SSOP and 56-pin QFN packages
• CY7C68301B is ideal for battery-powered designs
• CY7C68300B is ideal for self- and bus-powered designs
2.0
Block Diagram
SCL
RESET
I2C Bus Controller
SDA
Misc control signals
24
MHz
XTAL
PLL
ATA_EN (ATA Interface 3-state)
Internal Control Logic
ATA Interface
Control Signals
Control
ATA
Interface
Logic
16 Bit ATA Data
VBUS
D+
D-
USB 2.0 XCVR
CY Smart USB
FS/HS Engine
4kByte FIFO
Data
Figure 2-1. Block Diagram
Cypress Semiconductor Corporation
Document 38-08033 Rev. *D
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised February 21, 2005