CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
EP2–1024 double
(column 8).
buffered;
EP6–512
quad
buffered
EP0 IN&OUT
EP1 IN
EP1 OUT
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
EP2
512
512
EP2
512
512
EP2
512
512
EP2
512
512
EP2
512
512
EP2
512
512
EP2
1024
EP2
1024
EP2
1024
EP2
512
EP2 EP2
1024
1024
512
512
EP4
512
512
EP4
512
512
EP4
512
512
512
512
512
512
512
512
1024
1024
1024
EP6
512
1024
1024
EP6
512
512
EP6
512
512
EP6
1024
EP6
512
512
EP6
512
512
EP6
1024
EP6
512
512
EP6
512
512
EP6
1024
512
512
1024
1024
1024
EP8
512
512
512
512
1024
EP8
512
512
512
512
1024
EP8
512
512
512
512
1024
EP8
512
512
EP8
512
512
1024
1
2
3
4
5
6
7
8
9
10
11
12
Figure 3-5. Endpoint Configuration
3.12.5
Default Full-Speed Alternate Settings
Table 3-6. Default Full-Speed Alternate Settings
Alternate Setting
ep0
ep1out
ep1in
ep2
ep4
ep6
ep8
3.12.6
0
64
0
0
0
0
0
0
64
64 bulk
64 bulk
64 bulk out (2×)
64 bulk out (2×)
64 bulk in (2×)
64 bulk in (2×)
1
64
64 int
64 int
64 int out (2×)
64 bulk out (2×)
64 int in (2×)
64 bulk in (2×)
2
64
64 int
64 int
64 iso out (2×)
64 bulk out (2×)
64 iso in (2×)
64 bulk in (2×)
3
Default High-Speed Alternate Settings
Table 3-7. Default High-Speed Alternate Settings
Alternate Setting
ep0
ep1out
ep1in
ep2
ep4
ep6
ep8
64
0
0
0
0
0
0
0
64
512 bulk
512 bulk
512 bulk out (2×)
512 bulk out (2×)
512 bulk in (2×)
512 bulk in (2×)
1
64
64 int
64 int
512 int out (2×)
512 bulk out (2×)
512 int in (2×)
512 bulk in (2×)
2
64
64 int
64 int
512 iso out (2×)
512 bulk out (2×)
512 iso in (2×)
512 bulk in (2×)
3
Notes:
4. “0” means “not implemented.”
5. “2×” means “double buffered.”
6. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.
Document #: 38-08032 Rev. *K
Page 10 of 60
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