CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
10.2
Program Memory Read
t
CL
CLKOUT[17]
t
t
AV
AV
A[15..0]
t
t
STBH
STBL
PSEN#
D[7..0]
[18]
ACC1
t
DH
t
data in
t
SOEL
OE#
CS#
t
SCSL
Figure 10-1. Program Memory Read Timing Diagram
Table 10-1. Program Memory Read Parameters
Parameter Description
1/CLKOUT Frequency
Min.
Typ.
20.83
41.66
83.2
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
48 MHz
24 MHz
12 MHz
tCL
tAV
Delay from Clock to Valid Address
Clock to PSEN Low
Clock to PSEN High
Clock to OE Low
0
0
0
10.7
8
tSTBL
tSTBH
tSOEL
tSCSL
tDSU
tDH
8
11.1
13
Clock to CS Low
Data Set-up to Clock
Data Hold Time
9.6
0
Notes:
17. CLKOUT is shown with positive polarity.
18.
t
t
t
is computed from the above parameters as follows:
ACC1
ACC1
ACC1
(24 MHz) = 3*t – t – t
= 106 ns
= 43 ns.
CL
AV
DSU
DSU
(48 MHz) = 3*t – t – t
CL
AV
Document #: 38-08032 Rev. *K
Page 38 of 60
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