CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
9.10 Slave FIFO Asynchronous Write
Figure 9-10. Slave FIFO Asynchronous Write Timing Diagram
t
WRpwh
SLWR
SLWR/SLCS#
t
WRpwl
t
SFD
DATA
t
FDH
FLAGS
t
XFD
Table 24. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK
Parameter
t
WRpwl
t
WRpwh
t
SFD
t
FDH
t
XFD
SLWR pulse LOW
SLWR pulse HIGH
SLWR to FIFO DATA setup time
FIFO DATA to SLWR hold time
SLWR to FLAGS output propagation delay
Description
Min
50
70
10
10
–
Max
–
–
–
–
70
Unit
ns
ns
ns
ns
ns
9.11 Slave FIFO Synchronous Packet End Strobe
Figure 9-11. Slave FIFO Synchronous Packet End Strobe Timing Diagram
IFCLK
t
PEH
PKTEND
t
SPE
FLAGS
t
XFLG
Table 25. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK
Parameter
t
IFCLK
t
SPE
t
PEH
t
XFLG
IFCLK period
PKTEND to clock setup time
Clock to PKTEND hold time
Clock to FLAGS output propagation delay
Description
Min
20.83
14.6
0
–
Max
–
–
–
9.5
Unit
ns
ns
ns
ns
Table 26. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK
Parameter
t
IFCLK
t
SPE
t
PEH
t
XFLG
IFCLK period
PKTEND to clock setup time
Clock to PKTEND hold time
Clock to FLAGS output propagation delay
Description
Min
20.83
8.6
2.5
–
Max
200
–
–
13.5
Unit
ns
ns
ns
ns
Document #: 38-08032 Rev. *V
Page 47 of 66
CYPRESS [ CYPRESS SEMICONDUCTOR ]
