CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
9.9 Slave FIFO Synchronous Write
Figure 9-9. Slave FIFO Synchronous Write Timing Diagram
t
IFCLK
IFCLK
SLWR
t
SWR
t
WRH
DATA
Z
t
SFD
N
t
FDH
Z
FLAGS
t
XFLG
Table 22. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK
Parameter
t
IFCLK
t
SWR
t
WRH
t
SFD
t
FDH
t
XFLG
IFCLK period
SLWR to clock setup time
Clock to SLWR hold time
FIFO data to clock setup time
Clock to FIFO data hold time
Clock to FLAGS output propagation time
Description
Min
20.83
10.4
0
9.2
0
–
Max
–
–
–
–
–
9.5
Unit
ns
ns
ns
ns
ns
ns
Table 23. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK
Parameter
t
IFCLK
t
SWR
t
WRH
t
SFD
t
FDH
t
XFLG
IFCLK Period
SLWR to clock setup time
Clock to SLWR hold time
FIFO data to clock setup time
Clock to FIFO data hold time
Clock to FLAGS output propagation time
Description
Min
20.83
12.1
3.6
3.2
4.5
–
Max
200
–
–
–
–
13.5
Unit
ns
ns
ns
ns
ns
ns
Document #: 38-08032 Rev. *V
Page 46 of 66
CYPRESS [ CYPRESS SEMICONDUCTOR ]
