CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
9.16 Slave FIFO Asynchronous Address
Figure 9-17. Slave FIFO Asynchronous Address Timing Diagram
SLCS/FIFOADR [1:0]
t
SFA
SLRD/SLWR/PKTEND
t
FAH
Table 31. Slave FIFO Asynchronous Address Parameters
Parameter
t
SFA
t
FAH
Description
FIFOADR[1:0] to SLRD/SLWR/PKTEND setup time
RD/WR/PKTEND to FIFOADR[1:0] hold time
Min
10
10
Max
–
–
Unit
ns
ns
9.17 Sequence Diagram
9.17.1 Single and Burst Synchronous Read Example
Figure 9-18. Slave FIFO Synchronous Read Sequence and Timing Diagram
t
IFCLK
IFCLK
t
SFA
t
FAH
t
SFA
t
FAH
FIFOADR
t=0
t
SRD
t
RDH
T=0
>= t
SRD
>= t
RDH
SLRD
t=2
t=3
T=2
T=3
SLCS
t
XFLG
FLAGS
t
XFD
t
XFD
N+1
t
OEoff
t
OEon
N+1
N+2
t
XFD
N+3
t
XFD
N+4
DATA
Data Driven: N
t
OEon
t
OEoff
SLOE
t=4
t=1
T=1
T=4
Figure 9-19. Slave FIFO Synchronous Sequence of Events Diagram
IFCLK
IFCLK
IFCLK
IFCLK
IFCLK
IFCLK
IFCLK
IFCLK
IFCLK
IFCLK
FIFO POINTER
N
SLOE
N
SLRD
N+1
SLOE
SLRD
N+1
SLOE
N+1
SLRD
N+2
N+2
N+3
N+3
N+4
SLRD
N+4
SLOE
N+4
Not Driven
FIFO DATA BUS
Not Driven
Driven: N
N+1
Not Driven
N+1
N+4
N+4
Document #: 38-08032 Rev. *V
Page 50 of 66
CYPRESS [ CYPRESS SEMICONDUCTOR ]
