CY7C68013
LIST OF FIGURES
Figure 1-1. Block Diagram ....................................................................................................................... 6
Figure 3-1. Internal Code Memory, EA = 0 ............................................................................................ 12
Figure 3-2. External Code Memory, EA = 1........................................................................................... 13
Figure 3-3. Endpoint Configuration ........................................................................................................ 15
Figure 4-1. Signals................................................................................................................................. 19
Figure 4-2. CY7C68013 128-pin TQFP Pin Assignment ....................................................................... 20
Figure 4-3. CY7C68013 100-pin TQFP Pin Assignment ....................................................................... 21
Figure 4-4. CY7C68013 56-pin SSOP Pin Assignment ......................................................................... 22
Figure 4-5. CY7C68013 56-pin QFN Pin Assignment ........................................................................... 23
Figure 9-1. Program Memory Read Timing Diagram............................................................................. 38
Figure 9-2. Data Memory Read Timing Diagram ................................................................................... 39
Figure 9-3. Data Memory Write Timing Diagram ................................................................................... 40
Figure 9-4. GPIF Synchronous Signals Timing Diagram ....................................................................... 41
Figure 9-5. Slave FIFO Synchronous Read Timing Diagram ................................................................ 42
Figure 9-6. Slave FIFO Asynchronous Read Timing Diagram .............................................................. 43
Figure 9-7. Slave FIFO Synchronous Write Timing Diagram ................................................................ 43
Figure 9-8. Slave FIFO Asynchronous Write Timing Diagram............................................................... 44
Figure 9-9. Slave FIFO Synchronous Packet End Strobe Timing Diagram ........................................... 44
Figure 9-10. Slave FIFO Asynchronous Packet End Strobe Timing Diagram ....................................... 45
Figure 9-11. Slave FIFO Output Enable Timing Diagram ...................................................................... 45
Figure 9-12. Slave FIFO Address to Flags/Data Timing Diagram ......................................................... 45
Figure 9-13. Slave FIFO Synchronous Address Timing Diagram.......................................................... 46
Figure 9-14. Slave FIFO Asynchronous Address Timing Diagram ........................................................ 46
Figure 11-1. 56-lead Shrunk Small Outline Package O56 ..................................................................... 47
Figure 11-2. 56-lead Quad Flatpack No Lead Package (8 × 8 mm) LF56............................................. 47
Figure 11-3. 100-Pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A101 ......................................... 48
Figure 11-4. 128-Lead Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A128 ...................................... 49
Figure 13-1. Cross-section of the Area Underneath the QFN Package ................................................ 50
Figure 13-2. Plot of the Solder Mask (White Area) ................................................................................ 50
Figure 13-3. X-ray image of the assembly ............................................................................................. 51
Document #: 38-08012 Rev. *C
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CYPRESS [ CYPRESS SEMICONDUCTOR ]
