CY7C68013
Two memory maps are shown in the following diagrams:
Figure 3-1 Internal Code Memory, EA = 0
Figure 3-2 External Code Memory, EA = 1.
3.10.2 Internal Code Memory, EA = 0
This mode implements the internal eight-kbyte block of RAM (starting at 0) as combined code and data memory. When external
RAM or ROM is added, the external read and write strobes are suppressed for memory spaces that exist inside the chip. This
allows the user to connect a 64-kbyte memory without requiring address decodes to keep clear of internal memory spaces.
Only the internal eight kbytes and scratch pad 0.5 kbytes RAM spaces have the following access:
• USB download
• USB upload
• Setup data pointer
• I2C-compatible interface boot load.
Inside FX2
Outside FX2
FFFF
7.5 kbytes
(OK to populate
US B regs and
4k EP buffers
(RD#,WR#)
data memory
here—RD#/WR#
strobes are not
active)
E200
E1FF
0.5 kbytes RAM
Data (RD#,WR#)*
E000
56 kbytes
External
Code
Memory
(PSEN#)
48 kbytes
External
Data
Memory
(RD#,WR#)
1FFF
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
(OK to populate
program
memory here—
PSEN# strobe
is not active)
Eight kbytes RAM
Code and Data
(PSEN#,RD#,WR#)*
0000
Data
Code
*SUDPTR, USB upload/download, I2C-compatible interface boot access
Figure 3-1. Internal Code Memory, EA = 0
Document #: 38-08012 Rev. *C
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CYPRESS [ CYPRESS ]
