CY7C64713/14
EZ-USB FX1™ USB Microcontroller
Full-speed USB Peripheral Controller
1.0
Features
•
• Single-chip integrated USB transceiver, SIE, and
enhanced 8051 microprocessor
• Fit, form and function upgradable to the FX2LP
(CY7C68013A)
— Pin-compatible
— Object-code-compatible
— Functionally-compatible (FX1 functionality is a
Subset of the FX2LP)
• Draws no more than 65 mA in any mode making the FX1
suitable for bus powered applications
• Software: 8051 runs from internal RAM, which is:
— Downloaded via USB
— Loaded from EEPROM
— External memory device (128-pin configuration only)
• 16 KBytes of on-chip Code/Data RAM
• Four programmable BULK/INTERRUPT/ISOCH-
RONOUS endpoints
— Buffering options: double, triple, and quad
• Additional programmable (BULK/INTERRUPT) 64-byte
endpoint
• 8- or 16-bit external data interface
• Smart Media Standard ECC generation
• GPIF
— Allows direct connection to most parallel interfaces;
8- and 16-bit
— Programmable waveform descriptors and configu-
ration registers to define waveforms
24 MHz
Ext. XTAL
High-performance micro
using standard tools
with lower-power options
Address (16)
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— Supports multiple Ready (RDY) inputs and Control
(CTL) outputs
Integrated, industry standard 8051 with enhanced
features
— Up to 48-MHz clock rate
— Four clocks per instruction cycle
— Two USARTS
— Three counter/timers
— Expanded interrupt system
— Two data pointers
3.3V operation with 5V tolerant inputs
Smart SIE
Vectored USB interrupts
Separate data buffers for the Setup and DATA portions
of a CONTROL transfer
Integrated I
2
C controller, runs at 100 or 400 KHz
48-MHz, 24-MHz, or 12-MHz 8051 operation
Four integrated FIFOs
— Brings glue and FIFOs inside for lower system cost
— Automatic conversion to and from 16-bit buses
— Master or slave operation
— FIFOs can use externally supplied clock or
asynchronous strobes
— Easy interface to ASIC and DSP ICs
Vectored for FIFO and GPIF interrupts
Up to 40 general purpose I/Os
Three package options—128-pin TQFP, 100-pin TQFP,
and 56-pin QFN Lead-free
Data (8)
FX1
Address (16) / Data Bus (8)
VCC
x20
PLL
/0.5
/1.0
/2.0
8051 Core
12/24/48 MHz,
four clocks/cycle
I
2
C
Master
Additional I/Os (24)
1.5k
connected for
enumeration
D+
USB
D–
Integrated
full-speed XCVR
XCVR
CY
16 KB
RAM
Abundant I/O
including two USARTS
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, etc.
ADDR (9)
GPIF
ECC
RDY (6)
CTL (6)
Smart
USB
Engine
4 kB
FIFO
8/16
Up to 96 MBytes/s
burst rate
Enhanced USB core
Simplifies 8051 code
“Soft Configuration”
Easy firmware changes
FIFO and endpoint memory
(master or slave operation)
Figure 1-1. Block Diagram
Cypress Semiconductor Corporation
Document #: 38-08039 Rev. *B
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised February 14, 2005
CYPRESS [ CYPRESS SEMICONDUCTOR ]
