FOR
FOR
CY7C63000A/CY7C63001A
CY7C63100A/CY7C63101A
3.0
Name
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
XTALIN
XTALOUT
CEXT
D+
D–
V
PP
V
CC
V
SS
Pin Definitions
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
I/O
I/O
I/O
–
–
–
20-Pin
1
2
3
4
20
19
18
17
5
16
6
15
–
–
–
–
10
11
9
14
13
8
12
7
24-pin
1
2
3
4
24
23
22
21
5
20
6
19
7
18
8
17
12
13
11
16
15
10
14
9
Description
Port 0 bit 0
Port 0 bit 1
Port 0 bit 2
Port 0 bit 3
Port 0 bit 4
Port 0 bit 5
Port 0 bit 6
Port 0 bit 7
Port 1 bit 0
Port 1 bit 1
Port 1 bit 2
Port 1 bit 3
Port 1 bit 4
Port 1 bit 5
Port 1 bit 6
Port 1 bit 7
Ceramic resonator in
Ceramic resonator out
Connects to external R/C timing circuit for optional ‘suspend’ wakeup
USB data+
USB data–
Programming voltage supply, tie to ground during normal operation
Voltage supply
Ground
4.0
V
CC
V
SS
V
PP
XTALIN
Pin Description
Name
Description
1 pin. Connects to the USB power source or to a nominal 5V power supply. Actual V
CC
range can vary
between 4.0V and 5.25V.
1 pin. Connects to ground.
1 pin. Used in programming the on-chip EPROM. This pin should be tied to ground during normal operations.
1 pin. Input from an external ceramic resonator.
1 pin. Return path for the ceramic resonator (leave unconnected if driving XTALIN from an external oscilla-
tor).
16 pins. P0.0–P0.7 are the 8 I/O lines in Port 0. P1.0–P1.7 are the 8 I/O lines in Port 1. P1.0–P1.3 are
supported in the CY7C6300XA. All I/O pins include bit-programmable pull-up resistors. However, the sink
current of each pin can be programmed to one of sixteen levels. Besides functioning as GPIO lines, each
pin can be programmed as an interrupt input. The interrupt is edge-triggered, with programmable polarity.
2 pins. Bidirectional USB data lines. An external pull-up resistor must be connected between the D pin and
V
CC
to select low-speed USB operation.
1 pin. Open-drain output with Schmitt trigger input. The input is connected to a rising edge-triggered interrupt.
CEXT may be connected to an external RC to generate a wake-up from Suspend mode. See Section 5.4.
XTALOUT
P0.0–P0.7,
P1.0–P1.7
D+, D–
CEXT
Document #: 38-08026 Rev. **
Page 6 of 31
CYPRESS [ CYPRESS SEMICONDUCTOR ]
