CY7C419/21/25/29/33
into the FIFO, with a signal that is asynchronous to the read
signal. The (internal) state machine in the FIFO goes from empty
to empty+1. However, it does this asynchronously with respect
to the read signal, so that the effective pulse width of the read
signal cannot be determined, because the state machine does
not look at the read signal until it goes to the empty+1 state.
Similarly, the minimum write pulse width may be violated by
trying to write into a full FIFO, and asynchronously performing a
read. The empty and full flags are used to avoid these effective
pulse width violations, but to do this and operate at the maximum
frequency, the flag must be valid at the beginning of the next
cycle.
Figure 13. Depth Expansion
XO
W
FF
9
D
9
R
EF
9
Q
FL
CY7C419
CY7C420/1
CY7C424/5
CY7C428/9
CY7C432/3
V
CC
XI
XO
FULL
9
FF
EF
EMPTY
CY7C419
CY7C420/1
CY7C424/5
CY7C428/9
CY7C432/3
FL
XI
XO
*
FF
9
MR
CY7C419
CY7C420/1
CY7C424/5
CY7C428/9
CY7C432/3
EF
FL
XI
* FIRST DEVICE
Document #: 38-06001 Rev. *C
Page 12 of 17
CYPRESS [ CYPRESS SEMICONDUCTOR ]
