CY7C4801/4811/4821
CY7C4831/4841/4851
Switching Waveforms
(continued)
Reset Timing
RSA(RSB)
t
RSS
RENA1, RENA2
(RENB1,RENB2)
t
RSS
WENA1
(WENB1)
t
RSR
t
RSR
[12]
t
RS
t
RSS
[14]
t
RSR
WENA2/LDA
(WENB2/LDB)
EFA, PAEA
(EFB, PAEB)
FFA, PAFA
(FFB, PAFB)
t
RSF
t
RSF
t
RSF
QA
0
−
QA
8
(QB
0
−
QB
8
)
OEA(OEB)=1
[13]
OEA(OEB)=0
48X1–8
Notes:
12. The clocks (RCLKA,RCLKB, WCLKA,WCLKB) can be free-running during reset.
13. After reset, the outputs will be LOW if (OEA,OEB) = 0 and three-state if (OEA,OEB)=1.
14. Holding (WENA2/LDA,WENB2/LDB) HIGH during reset will make the pin act as a second enable pin. Holding(WENA2/LDA,WENB2/LDB) LOW during reset will make the
pin act as a load enable for the programmable flag offset registers.
Document #: 38-06005 Rev. **
Page 8 of 23
CYPRESS [ CYPRESS SEMICONDUCTOR ]
