CY7C4801/4811/4821
CY7C4831/4841/4851
transition of every write clock (WCLKA,WCLKB). Data is
stored is the RAM array sequentially and independently of any
on-going read operation.
Architecture
The CY7C48X1 functions as two independent FIFOs in a single
package, each with its own separate set of controls. The device con-
sists of two arrays of 256 to 8K words of 9 bits each (imple-
mented by a dual-port array of SRAM cells), two read pointers,
two write pointers, control signals (RCLKA, RCLKB, WCLKA,
WCLKB, RENA1, RENB1, RENA2, RENB2, WENA1, WENB1,
WENA2, WENB2, RSA, RSB), and flags (EFA,EFB, PAEA,PAEB,
PAFA,PAFB, FFA,FFB).
Write Enable 2/Load (WENA2/LDA, WENB2/LDB) - This is a
dual-purpose pin. The FIFO is configured at Reset to have
programmable flags or to have two write enables, which allows
for depth expansion. If Write Enable 2/Load (WENA2/LDA,
WENB2/LDB) is set active HIGH at Reset (RSA,RSB=LOW),
this pin operates as a second write enable pin.
If the FIFO is configured to have two write enables, when Write
Enable 1 (WENA1,WENB1) is LOW and Write Enable 2/Load
(WENA2/LDA, WENB2/LDB) is HIGH, data can be loaded into the
input register and RAM array on the LOW-to-HIGH transition of every
write clock (WCLKA,WCLKB). Data is stored in the RAM array se-
quentially and independently of any on-going read operation.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RSA,
RSB) cycle. This causes the FIFO to enter the Empty condition signi-
fied by (EFA,EFB) being LOW. All data outputs (QA0−8,QB0−8) go
LOW tRSF after the rising edge of RSA, RSB. In order for the FIFO to
reset to its default state, a falling edge must occur on (RSA,RSB) and
the user must not read or write while (RSA,RSB) is LOW. All flags are
guaranteed to be valid tRSF after (RSA,RSB) is taken LOW.
Programming
When (WENA2/LDA, WENB2/LDB) is held LOW during Reset, this
pin is the load (LDA,LDB) enable for flag offset programming. In this
configuration, (WENA2/LDA, WENB2/LDB) can be used to access
the four 8-bit offset registers contained in the CY7C48X1 for writing
or reading data to these registers.
FIFO Operation
When the (WENA1,WENB1) signal is active LOW and
(WENA2,WENB2) is active HIGH, data present on the
(DA0−8,DB0−8) pins is written into the FIFO on each rising edge
(WCLKA,WCLKB) of the (WCLKA,WCLKB) signal. Similarly, when
the (RENA1,RENB1) and (RENA2,RENB2) signals are active LOW,
When the device is configured for programmable flags and
both (WENA2/LDA, WENB2/LDB) and (WENA1,WENB1) are
LOW, the first LOW-to-HIGH transition of (WCLKA,WCLKB) writes
data from the data inputs to the empty offset least significant bit (LSB)
register. The second, third, and fourth LOW-to-HIGH transitions of
(WCLKA,WCLKB) store data in the empty offset most significant bit
(MSB) register, full offset LSB register, and full offset MSB register,
data in the FIFO memory will be presented on the (QA0−8,QB0−8
)
outputs. New data will be presented on each rising edge of
(RCLKA,RCLKB) while (RENA1,RENB1) and (RENA2,RENB2) are
active. (RENA1,RENB1) and (RENA2,RENB2) must set up tENS be-
fore (RCLKA,RCLKB) for it to be a valid read function.
(WENA1,WENB1) and (WENA2,WENB2) must occur tENS before
(WCLKA,WCLKB) for it to be a valid write function.
respectively,
when
(WENA2/LDA,
WENB2/LDB)
and
(WENA1,WENB1) are LOW. The fifth LOW-to-HIGH transition of
(WCLKA,WCLKB) while (WENA2/LDA, WENB2/LDB) and
(WENA1,WENB1) are LOW writes data to the empty LSB register
again. Figure 1 shows the register sizes and default values for the
various device types.
An output enable (OEA,OEB) pin is provided to three-state the
(QA0−8,QB0−8) outputs when (OEA,OEB) is asserted. When
(OEA,OEB) isenabled (LOW), data in the output register willbeavail-
able to the (QA0−8,QB0−8) outputs after tOE.
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the (WENA2/LDA, WENB2/LDB) input HIGH, the FIFO is returned
to normal read and write operation. The next time (WENA2/LDA,
WENB2/LDB) is brought LOW, a write operation stores data in the
next offset register in sequence.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its (QA0−8,QB0−8
)
outputs even after additional reads occur.
The contents of the offset registers can be read to the data
outputs when (WENA2/LDA, WENB2/LDB) is LOW and both
(RENA1,RENB1) and (RENA2,RENB2) are LOW. LOW-to-HIGH
transitions of (RCLKA,RCLKB) read register contents to the data out-
puts. Writes and reads should not be preformed simultaneously on
the offset registers.
Write Enable 1 (WENA1,WENB1) - If the FIFO is configured
for programmable flags, Write Enable 1 (WENA1,WENB1) is
the only write enable control pin. In this configuration, when
Write Enable 1 (WENA1,WENB1) is LOW, data can be loaded
into the input register and RAM array on the LOW-to-HIGH
Document #: 38-06005 Rev. **
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