CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms (continued)
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
t
DS
D0–D8
VALIDWrite)
D
2
D
3
D
4
D0(FIRST
D
1
t
ENS
[19]
FRL
t
WEN1
WEN2
(if applicable)
t
SKEW1
RCLK
t
REF
EF
[20]
tA
t
A
REN1,
REN2
Q0–Q
D
0
D
1
8
t
OLZ
t
OE
OE
Empty Flag Timing
WCLK
t
t
DS
DS
DATAWRITE2
DATAWRITE1
D –D
0
8
t
t
ENH
ENH
t
t
ENS
t
t
ENS
WEN1
WEN2
(if applicable)
ENS
t
t
ENS
ENH
ENH
[19]
[19]
t
t
FRL
FRL
RCLK
t
t
t
REF
t
t
SKEW1
REF
REF
SKEW1
EF
REN1,
REN2
LOW
OE
t
A
DATA IN OUTPUT REGISTER
DATA Read
Q –Q
0
8
Notes:
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable
for the programmable flag offset registers.
18. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
19. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or
tCLK + tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW).
20. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06016 Rev. *A
Page 10 of 18
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