CY7C419/21/25/29/33
Switching Waveforms
(continued)
Expansion Timing Diagrams
WRITE TO LAST PHYSICAL
LOCATION OF DEVICE 1
W
t
WR
[15]
WRITE TO FIRST PHYSICAL
LOCATION OF DEVICE 2
t
XOL
t
XOH
XO
1
(XI
2
)
t
SD
D
0
–D
8
t
HD
t
SD
t
HD
DATA VALID
DATA VALID
C420–17
READ FROM LAST PHYSICAL
LOCATION OF DEVICE 1
R
t
RR
t
XOL
t
XOH
READ FROM FIRST PHYSICAL
LOCATION OF DEVICE 2
XO
1
(XI
2
)
[15]
t
HZR
t
LZR
Q
0
–Q
8
t
A
t
DVR
DATA
VALID
t
A
t
DVR
DATA
VALID
C420–18
Note:
15. Expansion Out of device 1 (XO
1
) is connected to Expansion In of device 2 (XI
2
).
Architecture
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9,
CY7C432/3 FIFOs consist of an array of 256, 512, 1024, 2048,
4096 words of 9 bits each (implemented by an array of du-
al-port RAM cells), a read pointer, a write pointer, control sig-
nals (W, R, XI, XO, FL, RT, MR), and Full, Half Full, and Empty
flags.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory
cell used in the RAM. The cell itself enables the read and write
operations to be independent of each other, which is neces-
sary to achieve truly asynchronous operation of the inputs and
outputs. A second benefit is that the time required to increment
the read and write pointers is much less than the time that
would be required for data propagation through the memory,
which would be the case if the memory were implemented
using the conventional register array architecture.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the empty condition
signified by the Empty flag (EF) being LOW, and both the Half
Full (HF) and Full flags (FF) being HIGH. Read (R) and write
(W) must be HIGH t
RPW
/t
WPW
before and t
RMR
after the rising
edge of MR for a valid reset cycle. If reading from the FIFO
after a reset cycle is attempted, the outputs will all be in the
high-impedance state.
Document #: 38-06001 Rev. *A
Page 11 of 22
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