CY7C1021CV33
Switching Characteristics
Over the Operating Range
[5]
1021CV33-8
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU[8]
t
PD[8]
t
DBE
t
LZBE
t
HZBE
Write
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Cycle
[9]
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to
Low-Z
[6]
WE LOW to High-Z
[6, 7]
Byte Enable to End of Write
6
8
7
7
0
0
6
5
0
3
4
7
10
8
8
0
0
7
5
0
3
5
8
12
9
9
0
0
8
6
0
3
6
9
15
10
10
0
0
10
8
0
3
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[6]
OE HIGH to High-Z
[6, 7]
CE LOW to
CE HIGH to
Low-Z
[6]
High-Z
[6, 7]
0
8
5
0
4
0
5
3
4
0
10
5
0
6
0
4
3
5
0
12
6
0
7
3
8
5
0
5
3
6
0
15
7
8
8
3
10
5
0
6
3
7
10
10
3
12
6
0
7
12
12
3
15
7
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
1021CV33-10
Min.
Max.
1021CV33-12
Min.
Max.
1021CV33-15
Min.
Max.
Unit
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZBE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
8. This parameter is guaranteed by design and is not tested.
9. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write,
and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
Document #: 38-05132 Rev. *C
Page 5 of 12
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