CY7C188
Switching Characteristics
Over the Operating Range
[2, 5]
7C188–15
Parameter
Description
Min.
Max.
7C188–20
Min.
Max.
7C188–25
Min.
Max.
7C188–35
Min.
Max.
Unit
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. The internal write time of the memory is defined by the overlap of CE
1
, LOW, CE
2
HIGH, and WE LOW. All three signals must be asserted to initiate a write and any
signal can terminate a write by being deasserted. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Switching Waveforms
Read Cycle No. 1
[10,11]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
C188–5
Read Cycle No. 2 (Chip-Enable Controlled)
[11,12,13]
t
RC
CE
1
t
ACE
OE
t
DOE
t
LZOE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
PD
ICC
50%
ISB
C188–6
t
HZOE
t
HZCE
DATA VALID
HIGH
IMPEDANCE
DATA OUT
Write Cycle No. 1 (WE Controlled)
[8,13,14,15]
Document #: 38-05053 Rev. **
Page 4 of 8
CYPRESS [ CYPRESS SEMICONDUCTOR ]
