CY7C188
Switching Waveforms
(Continued)
t
WC
ADDRESS
CE
1
t
AW
t
SA
WE
OE
t
SD
DATA I/O
NOTE 16
t
HZOE
Notes:
10. Device is continuously selected. OE, CE = V
IL
.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
13. Timing parameters are the same for all chip enable signals (CE
1
and CE
2
), so only the timing for CE
1
is shown.
14. Data I/O is high impedance if OE = V
IH
.
15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
16. During this period, the I/Os are in the output state and input signals should not be applied.
[8,13,14,15]
t
HA
t
PWE
t
HD
DATA
IN
VALID
C188–7
Write Cycle No.2 (CE Controlled)
t
WC
ADDRESS
t
SCE
CE
1
t
SA
t
AW
t
HA
WE
t
SD
DATA I/O
DATA
IN
VALID
C188–8
t
HD
Write Cycle No. 3 (WE Controlled, OE LOW)
[9,13,15]
Document #: 38-05053 Rev. **
Page 5 of 8
CYPRESS [ CYPRESS SEMICONDUCTOR ]
