CY7C187
Switching Waveforms
Read Cycle No. 2
[10, 12]
t
RC
CE
t
ACE
t
LZCE
DATA OUT
HIGH IMPEDANCE
DATA VALID
t
PD
ICC
50%
50%
ISB
C187–7
t
HZCE
HIGH
IMPEDANCE
V
CC
SUPPLY
CURRENT
t
PU
Write Cycle No. 1 (WE Controlled)
[11]
t
WC
ADDRESS
t
SCE
CE
t
SA
WE
t
SD
DATA IN
DATA VALID
t
HZWE
DATA OUT
DATA UNDEFINED
C187–8
t
AW
t
PWE
t
HA
t
HD
t
LZWE
HIGH IMPEDANCE
Write Cycle No. 2 (CE Controlled)
[11, 13]
t
WC
ADDRESS
t
SA
CE
t
AW
t
PWE
WE
t
SD
DATA IN
DATA VALID
t
HD
t
HA
t
SCE
DATA OUT
Notes:
12. Address valid prior to or coincident with CE transition LOW.
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
HIGH IMPEDANCE
C187–9
Document #: 38-05044 Rev. **
Page 5 of 9
CYPRESS [ CYPRESS SEMICONDUCTOR ]
